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PCI9060ES Datasheet(PDF) 133 Page - List of Unclassifed Manufacturers

Part # PCI9060ES
Description  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PDF  192 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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PCI9060ES Datasheet(HTML) 133 Page - List of Unclassifed Manufacturers

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SECTION 8
PCI 9080
TIMING DIAGRAMS
©PLX Technology, Inc., 1997
Page 124
Version 1.02
CMD
BE
ADDR
AA
LBE
RETRY
A
CMD
CMD
BE
WRITE IS NOT ALLOWED DURING DELAYED READ
RETRY
Delayed Read Retries
D0
D1
D2
D3
D4
D5
D6
D7
D8
READS DATA
+4
+8
+C
+10 +14 +18
+1C
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15
+20 +24
+28 +2C +30 +34 +38 +3C
ADDR
CMD
D0
BE
WRITE RETRIES AND
COMPLETES
0ns
250ns
500ns
750ns
1000ns
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
DEVSEL#
TRDY#
PERR#
STOP#
LCLK
LHOLD
LHOLDA
ADS#
BLAST#
LA[31:0]
LAD[31:0]
LBE[3:0]#
READYi#
LW/R#
Disconnect immediately for a read.
Don’t effect pending reads when a write cycle occurs.
Don’t flush the read FIFO if the PCI read cycle completes.
Force Retry on write if read pending.
Negate TRDY# until space is available in the direct slave write FIFO.
Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec



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