MSC1210 datasheet(44/83 Pages) TI

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MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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External Interrupt Flag (EXIF)

Reset Value

SFR 91h

IE5

IE4

IE3

IE2

08h

IE5

External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared

bit 7

manually by software. Setting this bit in software will cause an interrupt if enabled.

IE4

External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared

bit 6

manually by software. Setting this bit in software will cause an interrupt if enabled.

IE3

External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared

bit 5

manually by software. Setting this bit in software will cause an interrupt if enabled.

IE2

External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared

bit 4

manually by software. Setting this bit in software will cause an interrupt if enabled.

Memory Page (MPAGE)

Reset Value

SFR 92h

00h

MPAGE

The 8051 uses Port 2 for the upper 8 bits of the external data memory access by MOVX A,@Ri and MOVX @Ri,A

bits 7−0

instructions. The MSC1210 uses register MPAGE instead of Port 2. To access external data memory using the MOVX

A,@Ri

and MOVX @Ri,A instructions, the user should preload the upper byte of the address into MPAGE (versus

preloading into P2 for the standard 8051).

Configuration Address Register (CADDR) (write-only)

Reset Value

SFR 93h

00h

CADDR

Configuration Address Register. This register supplies the address for reading bytes in the 128 bytes of Flash

bits 7−0

Configuration memory. This is a write-only register.

CAUTION:

If this register is written to while executing from Flash Memory, the CDATA register will be incorrect.

The faddr_data_read routine in the Boot ROM can be used for this purpose.

Configuration Data Register (CDATA) (read-only)

Reset Value

SFR 94h

00h

CDATA

Configuration Data Register. This register will contain the data in the 128 bytes of Flash Configuration memory that

bits 7−0

are located at the last written address in the CADDR register. This is a read-only register.

MSC1210 Datasheet(PDF) 44 Page - Texas Instruments

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