MSC1210 datasheet(38/83 Pages) TI

38 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

www.ti.com

Port 0 (P0)

Reset Value

SFR 80h

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

FFh

P0.7−0

Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general-

bits 7−0

purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain

the LSB of the address when ALE is HIGH, and Data when ALE is LOW. When used as a general-purpose I/O, this

port drive is selected by P0DDRL and P0DDRH (ACh, ADh). Whether Port 0 is used as general-purpose I/O or for

external memory access is determined by the Flash Configuration Register (HCR1.1)

Stack Pointer (SP)

Reset Value

SFR 81h

SP.7

SP.6

SP.5

SP.4

SP.3

SP.2

SP.1

SP.0

07h

SP.7−0

Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented

bits 7−0

before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07h

after reset.

Data Pointer Low 0 (DPL0)

Reset Value

SFR 82h

DPL0.7

DPL0.6

DPL0.5

DPL0.4

DPL0.3

DPL0.2

DPL0.1

DPL0.0

00h

DPL0.7−0

Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are

bits 7−0

used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).

Data Pointer High 0 (DPH0)

Reset Value

SFR 83h

DPH0.7

DPH0.6

DPH0.5

DPH0.4

DPH0.3

DPH0.2

DPH0.1

DPH0.0

00h

DPH0.7−0

Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are

bits 7−0

used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86h).

Data Pointer Low 1 (DPL1)

Reset Value

SFR 84h

DPL1.7

DPL1.6

DPL1.5

DPL1.4

DPL1.3

DPL1.2

DPL1.1

DPL1.0

00h

DPL1.7−0

Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0,

bits 7−0

SFR 86h) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations.

MSC1210 Datasheet(PDF) 38 Page - Texas Instruments

MSC1210 Datasheet(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL