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MSC1210 Datasheet(PDF) 26 Page - Texas Instruments

Part # MSC1210
Description  Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash Memory
PDF  83 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSC1210 Datasheet(HTML) 26 Page - Texas Instruments

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MSC1210
SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004
www.ti.com
26
BROWNOUT RESET
The brownout reset (BOR) is enabled through Hardware
Configuration Register 1 (HCR1). If the conditions for
proper POR are not met or the device encounters a
brownout condition that does not generate a POR, the
BOR can be used to ensure proper device operation. The
BOR will hold the state of the device when the power
supply drops below the threshold level programmed in
HCR1, and then generate a reset when the supply rises
above the threshold level. Note that as the device is
released from reset, and program execution begins, the
device current consumption may increase, which may
result in a power-supply voltage drop, which may initiate
another brownout condition.
The BOR level should be chosen to match closely with the
application. For example, with a high external clock
frequency, the BOR level should match the minimum
operating voltage range for the device, or improper
operation may still occur.
Note that AVDD must rise above 2.0V for the Analog
Brownout Reset function to be disabled; otherwise, it will
be enabled and hold the device in reset.
POWER-DOWN MODES
The MSC1210 can power several of the on-chip
peripherals and put the CPU into IDLE. This is
accomplished by shutting off the clocks to those sections,
as shown in Figure 17. For lowest power, be sure that the
FRCM bit in FMCON is set.
USEC
FB
MSECH
HMSEC
FE
MSINT
FA
ACLK
F6
divide
by 64
MSECL
FD
FC
ms
µs
100ms
Flash Write
Timing
Flash Erase
Timing
WDTCON
SECINT
F9
FF
FTCON
[3:0]
FTCON
[7:4]
EF
EF
seconds
interrupt
watchdog
milliseconds
interrupt
ADC Output Rate
ADCON3
ADCON2
DF
DE
Decimation Ratio
SYS Clock
Oscillator
PWMHI
PWMLOW
A3
A2
PWM Clock
SPICON
9A
SCK
t
CLK
(30
µsto 40µs)
(5ms to 11ms)
STOP
PDCON.0
PDCON.4
PDCON.1
PDCON.2
PDCON.3
IDLE
CPU Clock
Timers 0/1/2
ADC Power Down
USART0/1
ADCON0
DC
f
SAMP
f
MOD
(see Figure 13)
Figure 17. MSC1210 Timing Chain and Clock Control



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