MSC1210 datasheet(46/83 Pages) TI

46 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

www.ti.com

Serial Data Buffer 0 (SBUF0)

Reset Value

SFR 99h

00h

SBUF0

Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive

bits 7−0

buffers are separate registers, but both are addressed at this location.

SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers. PDCON controls which

is enabled.

Reset Value

SFR 9Ah

SCK2

SCK1

SCK0

ORDER

MSTR

CPHA

CPOL

00h

SCK

SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.

bits 7−5

SCK2

SCK1

SCK0

SCK PERIOD

tCLK/2

tCLK/4

tCLK/8

tCLK/16

tCLK/32

tCLK/64

tCLK/128

tCLK/256

ORDER

Set Bit Order for Transmit and Receive.

bit 3

0: Most Significant Bits First

1: Least Significant Bits First

MSTR

SPI Master Mode.

bit 2

0: Slave Mode

1: Master Mode

CPHA

Serial Clock Phase Control.

bit 1

0: Valid data starting from half SCK period before the first edge of SCK

1: Valid data starting from the first edge of SCK

CPOL

Serial Clock Polarity.

bit 0

0: SCK idle at logic LOW

1: SCK idle at logic HIGH

SPI Data Register (SPIDATA)

Reset Value

SFR 9Bh

00h

SPIDATA

SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are

bits 7−0

separate registers, but both are addressed at this location. Read to clear the receive interrupt and write to clear the

transmit interrupt.

MSC1210 Datasheet(PDF) 46 Page - Texas Instruments

MSC1210 Datasheet(HTML) 46 Page - Texas Instruments

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