MSC1210 datasheet(27/83 Pages) TI

27 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

www.ti.com

MEMORY MAP

The MSC1210 contains on-chip SFR, Flash Memory,

Scratchpad SRAM Memory, Boot ROM, and SRAM. THe

SFR registers are primarily used for control and status.

The standard 8051 features and additional peripheral

features of the MSC1210 are controlled through the SFR.

Reading from an undefined SFR and writing to undefined

SFR registers is not recommended, and will have

indeterminate effects.

Flash Memory is used for both Program Memory and Data

Memory. The user has the ability to select the partition size

of Program and Data Memories. The partition size is set

through

hardware

configuration

bits,

which

are

programmed

through

either

the

parallel

serial

programming methods. Both Program and Data Flash

Memories are erasable and writable (programmable) in

User

Application mode (UAM). However, program

execution can only occur from Program Memory. As an

added precaution, a lock feature can be activated through

the hardware configuration bits, which disables erase and

writes to 4kB of Program Flash Memory or the entire

Program Flash Memory in UAM.

The MSC1210 includes 1kB of SRAM on-chip. SRAM

starts at address 0 and is accessed through the MOVX

instruction. This SRAM can also be located to start at

8400h and can be accessed as both Program and Data

Memory.

FLASH MEMORY

The MSC1210 uses a memory addressing scheme that

separates Program Memory (FLASH/ROM) from Data

Memory (FLASH/RAM). Each area is 64kB beginning at

address 0000h and ending at FFFFh, as shown in

Figure 18. The program and data segments can overlap

since they are accessed in different ways. Program

Memory is fetched by the microcontroller automatically.

There is one instruction (MOVC) that is used to explicitly

read the program area. This is commonly used to read

lookup tables.

The Data Memory area is accessed explicitly using the

MOVX instruction. This instruction provides multiple ways

of specifying the target address. It is used to access the

64kB of Data Memory. The address and data range of

devices with on-chip Program and Data Memory overlap

the 64kB memory space. When on-chip memory is

enabled, accessing memory in the on-chip range will

cause the device to access internal memory. Memory

accesses beyond the internal range will be addressed

externally via Ports 0 and 2.

The MSC1210 has two Hardware Configuration registers

(HCR0 and HCR1) that are programmable only during

Flash Memory Programming mode.

1k RAM or External

External Memory

0000h, 0k

2000h, 8k (Y3)

1000h, 4k (Y2)

4000h, 16k (Y4)

8400h, 33k (Y5)

8000h, 32k (Y5)

2k Internal Boot ROM

F800h

FFFFh

External

Program

Memory

Can Be Mapped to

Either Memory Space

8800h

0400h, 1k

1400h, 5k (Y2)

2400h, 9k (Y3)

4400h, 17k (Y4)

8400h, 33k (Y5)

FFFFh

External

Data

Memory

Program

Memory

Data

Memory

8800h

On−Chip

Flash

On−Chip

Flash

Figure 18. Memory Map

MSC1210 Datasheet(PDF) 27 Page - Texas Instruments

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