MSC1210 datasheet(79/83 Pages) TI

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MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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Seconds Timer Interrupt (SECINT)

Reset Value

SFR F9h

WRT

SECINT6

SECINT5

SECINT4

SECINT3

SECINT2

SECINT1

SECINT0

7Fh

This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then, the 1ms timer tick is divided by the

an interrupt that occurs from 100ms to 12.8 seconds. Reading this register clears the Seconds Interrupt. This Interrupt can

be monitored in the AIE register.

WRT

Write Control. Determines whether to write the value immediately or wait until the current count is finished.

bit 7

Read = 0.

0 = Delay Write Operation. The SEC value is loaded when the current count expires.

1 = Write Immediately. The counter is loaded once the CPU completes the write operation.

SECINT6−0 Seconds Count. Normal operation uses 100ms as the clock interval, and would equal: (SEC + 1)/10 seconds.

bits 6−0

Seconds Interrupt = (1 + SEC)

• (HMSEC + 1) • (MSEC + 1) • tCLK

Milliseconds Interrupt (MSINT)

Reset Value

SFR FAh

WRT

MSINT6

MSINT5

MSINT4

MSINT3

MSINT2

MSINT1

MSINT0

7Fh

The clock used for this timer is the 1ms clock, which results from dividing the system clock by the values in registers

MSECH:MSECL. Reading this register clears the interrupt.

WRT

Write Control. Determines whether to write the value immediately or wait until the current count is finished.

bit 7

Read = 0.

0 = Delay Write Operation. The MSINT value is loaded when the current count expires.

1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.

MSINT6−0

Seconds Count. Normal operation would use 1ms as the clock interval.

bits 6−0

MS Interrupt Interval = (1 + MSINT)

• (MSEC + 1) • tCLK

One Microsecond Register (USEC)

Reset Value

SFR FBh

FREQ4

FREQ3

FREQ2

FREQ1

FREQ0

03h

FREQ4−0

Clock Frequency − 1. This value + 1 divides the system clock to create a 1

µs clock.

bits 4−0

USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFh).

One Millisecond Low Register (MSECL)

Reset Value

SFR FCh

MSECL7

MSECL6

MSECL5

MSECL4

MSECL3

MSECL2

MSECL1

MSECL0

9Fh

MSECL7−0 One Millisecond Low. This value in combination with the next register is used to create a 1ms clock.

bits 7−0

1ms = (MSECH

• 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFh).

MSC1210 Datasheet(PDF) 79 Page - Texas Instruments

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