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MSC1210 Datasheet(PDF) 23 Page - Texas Instruments

Part # MSC1210
Description  Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash Memory
PDF  83 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSC1210 Datasheet(HTML) 23 Page - Texas Instruments

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MSC1210
SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004
www.ti.com
23
A
IN3
A
IN4
A
IN5
A
IN6
A
IN0
A
IN1
A
IN2
A
IN7
A
IN CO M
Burnout Detect
Current Source
Burnout Detect
Current Sink
AGND
Temperature Sensor
I
80
• I
AV
DD
In+
In
−
Figure 12. Input Multiplexer Configuration
BURNOUT DETECT
When the Burnout Detect (BOD) bit is set in the ADC
control configuration register (ADCON0 DCh), two current
sources are enabled. The current source on the positive
input channel sources approximately 2
µA of current. The
current source on the negative input channel sinks
approximately 2
µA. This allows for the detection of an
open circuit (full-scale reading) or short circuit (small
differential reading) on the selected input differential pair.
Buffer should be on for sensor burnout detection.
INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always
preferred.
The input impedance of the MSC1210 without the buffer is
7M
Ω/PGA. The buffer is controlled by the state of the BUF
bit in the ADC control register (ADCON0 DCh).
ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6h) and gain (PGA). The relationship is:
A
IN Impedance(W) +
1
ACLK Frequency
@ 7MW
PGA
where ACLK frequency
+
f
OSC
(ACLK
)1)
and
modclk
+ f
MOD +
f
ACLK
64
.
NOTE: The input impedance for PGA = 128 is the same as that for
PGA = 64 (
that is,
7M
W
64
).
Figure 13 shows the basic input structure of the MSC1210.
R
switch
(3k typical)
C
S
AGND
A
IN
High Impedance
>1G
Ω
PGA
f
SAMP
1, 2, 4
modclk
8
2 * modclk
16
4 * modclk
32
8 * modclk
64, 128
16 * modclk
PGA
C
S
1
9pF
2
18pF
4to128
36pF
Sampling
Frequency = fSAMP
(9pF typical)
Figure 13. Analog Input Structure
MODULATOR
The modulator is a single-loop 2nd-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the CLK using the value in the Analog Clock (ACLK)
register (SFR F6h). The data rate is:
Data Rate
+
f
MOD
Decimation Ratio
where f
MOD +
f
OSC
(ACLK
)1) @ 64



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