MSC1210 datasheet(31/83 Pages) TI

31 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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In any case, the low byte of the address is time-multiplexed

with the data byte on Port 0. The ADDR/DATA signals use

CMOS drivers in the Port 0, Port 2, WR, and RD output

buffers. Thus, in this application the Port 0 pins are not

open-drain outputs, and do not require external pull-ups for

high-speed access. Signal ALE (Address Latch Enable)

should be used to capture the address byte into an external

latch. The address byte is valid at the negative transition

of ALE. Then, in a write cycle, the data byte to be written

appears on Port 0 just before WR is activated, and remains

there until after WR is deactivated. In a read cycle, the

incoming byte is accepted at Port 0 just before the read

strobe is deactivated.

The functions of Port 0 and Port 2 are selected in Hardware

Configuration Register 1. This can only be changed during

the Flash Program mode. There is no conflict in the use of

these

registers;

they

will

either

used

general-purpose I/O or for external memory access. The

default state is for Port 0 and Port 2 to be used as

general-purpose I/O. If an external memory access is

attempted when they are configured as general-purpose

I/O, the values of Port 0 and Port 2 will not be affected.

External Program Memory is accessed under two

conditions:

Whenever signal EA is LOW during reset, then all

future accesses are external; or

Whenever the Program Counter (PC) contains a

number that is outside of the internal Program

Memory address range, if the ports are enabled.

If Port 0 and Port 2 are selected for external memory, all 8

bits of Port 0 and Port 2, as well as P3.6 and P3.7, are

dedicated to an output function and may not be used for

general-purpose I/O. During external program fetches,

Port 2 outputs the high byte of the PC.

Programming Flash Memory

There are four sections of Flash Memory for programming:

128 configuration bytes.

Reset sector (4kB) (not to be confused with the 2kB

Boot ROM).

Program Memory.

Data Memory.

Boot ROM

There is a 2kB Boot ROM that controls operation during

serial or parallel programming. Additionally, the Boot ROM

routines can be accessed during the user mode if it is

enabled. When enabled, the Boot ROM routines will be

located at memory addresses F800h−FFFFh during user

mode. In program mode the Boot ROM is located in the first

2kB of Program Memory. For additional information, refer

to the Application Note SBAA085, available for download

from the TI web site (www.ti.com).

Flash Programming Mode

There are two programming modes: parallel and serial. The

programming mode is selected by the state of the ALE and

PSEN signals during power-on reset. Serial programming

mode is selected with PSEN = 0 and ALE = 1. Parallel

programming mode is selected with PSEN = 1 and ALE = 0

(see Figure 21). If they are both HIGH, the MSC1210 will

operate in normal user mode. Both signals LOW is a

reserved mode and is not defined. Programming mode is

exited with a reset (BOR, WDT, software, or POR) and the

normal mode selected.

PSEN

ALE

MSC1210

HOST

Flash

Programmer

P2[7]

P2[6:0]

P1[7:0]

P0[7:0]

P3[7:5]

P3[4]

P3[3]

P3[2]

RST

XIN

PSEL

AddrHi[6:0]

AddrLo[7:0]

Data[7:0]

Cmd[2:0]

Req

ACK

Pass

RST

CLK

Figure 21. Parallel Programming Configuration

The MSC1210 is shipped with Flash Memory erased (all

1s). Parallel programming methods typically involve a

third-party programmer. Serial programming methods

typically involve in-system programming. UAM allows

Flash Program and Data Memory programming. The

actual code for Flash programming cannot execute from

Flash. That code must execute from the Boot ROM,

internal (von Neumann) RAM or external memory.

MSC1210 Datasheet(PDF) 31 Page - Texas Instruments

MSC1210 Datasheet(HTML) 31 Page - Texas Instruments

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