MSC1210 datasheet(73/83 Pages) TI

73 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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Summation Register 0 (SUMR0)

Reset Value

SFR E2h

00h

SUMR0

Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7.

bits 7−0

Write: Will cause values in SUMR3−0 to be added to the summation register.

Read: Will clear the Summation Count Interrupt.

Summation Register 1 (SUMR1)

Reset Value

SFR E3h

00h

SUMR1

Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8−15.

bits 7−0

Summation Register 2 (SUMR2)

Reset Value

SFR E4h

00h

SUMR2

Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16−23.

bits 7−0

Summation Register 3 (SUMR3)

Reset Value

SFR E5h

00h

SUMR3

Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24−31.

bits 7−0

Offset DAC Register (ODAC)

Reset Value

SFR E6h

00h

ODAC

Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset DAC

bits 7−0

value is summed with the ADC input prior to conversion. Writing 00h or 80h to ODAC turns off the offset DAC.

bit 7

Offset DAC Sign bit.

0 = Positive

1 = Negative

bit 6−0

Offset

REF

@ PGA @

ODAC 6: 0

127

@ (* 1)

bit7

NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals.

MSC1210 Datasheet(PDF) 73 Page - Texas Instruments

MSC1210 Datasheet(HTML) 73 Page - Texas Instruments

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