MSC1210 datasheet(24/83 Pages) TI

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MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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PGA

The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.

Using the PGA can actually improve the effective

resolution of the ADC. For instance, with a PGA of 1 on a

±2.5V full-scale range, the ADC can resolve to 1.5µV. With

a PGA of 128 on a

±19mV full-scale range, the ADC can

resolve to 75nV, as shown in Table 2.

Table 2. ENOB versus PGA (Bipolar Mode)

PGA

SETTING

FULL-SCALE

RANGE (V)

ENOB

AT 10HZ

RMS

MEASUREMENT

RESOLUTION (nV)

±2.5V

21.7

1468

±1.25

21.5

843

±0.625

21.4

452

±0.313

21.2

259

±0.156

20.8

171

±0.0781

20.4

113

±0.039

74.5

128

±0.019

74.5

OFFSET DAC

The analog input to the PGA can be offset by up to half the

full-scale input range of the PGA by using the ODAC

8-bit value; the MSB is the sign and the seven LSBs

provide the magnitude of the offset. Since the ODAC

introduces an analog (instead of digital) offset to the PGA,

using the ODAC does not reduce the range of the ADC.

CALIBRATION

The offset and gain errors in the MSC1210, or the

complete system, can be reduced with calibration.

Calibration is controlled through the ADCON1 register

(SFR DDh), bits CAL2:CAL0. Each calibration process

takes seven tDATA (data conversion time) periods to

complete. Therefore, it takes 14 tDATA periods to complete

both an offset and gain calibration.

For system calibration, the appropriate signal must be

applied to the inputs. The system offset command requires

a zero differential input signal. It then computes an offset

value that will nullify offsets in the system. The system gain

command requires a positive full-scale differential input

signal. It then computes a value to nullify gain errors in the

system. Each of these calibrations will take seven tDATA

periods to complete.

Calibration should be performed after power on, a change

in temperature, decimation ratio, buffer, or a change of the

PGA. Calibration will remove the effects of the Offset DAC;

therefore, changes to the Offset DAC register must be

done after calibration.

At the completion of calibration, the ADC Interrupt bit goes

HIGH which indicates the calibration is finished and valid

data is available.

DIGITAL FILTER

The Digital Filter can use either the Fast Settling, Sinc2, or

Sinc3 filter, as shown in Figure 14. In addition, the Auto

mode changes the Sinc filter after the input channel or

PGA is changed. When switching to a new channel, it will

use the Fast Settling filter for the next two conversions (the

first of which should be discarded). It will then use the Sinc2

followed by the Sinc3 filter to improve noise performance.

Adjustable Digital Filter

Data Out

Modulator

Fast Settling

Sinc2

Sinc3

Discard

Fast

Sinc2

Sinc3

FILTER

SETTLING TIME

(Conversion Cycles)(1)

Sinc3

Sinc2

Fast

NOTE: (1) MUX change may add one cycle.

CONVERSION CYCLE

AUTO MODE FILTER SELECTION

FILTER SETTLING TIME

Figure 14. Filter Step Responses

This combines the low-noise advantage of the Sinc3 filter

with the quick response of the Fast Settling Time filter. The

frequency response of each filter is shown in Figure 15.

MSC1210 Datasheet(PDF) 24 Page - Texas Instruments

MSC1210 Datasheet(HTML) 24 Page - Texas Instruments

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