MSC1210 datasheet(78/83 Pages) TI

78 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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Analog Clock (ACLK)

Reset Value

SFR F6h

FREQ6

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

FREQ0

03h

FREQ6−0

Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock.

bit 6−0

ACLK frequency

CLK

FREQ

) 1

MOD +

CLK

(ACLK ) 1) @ 64

Data Rate

MOD

Decimation

System Reset Register (SRST)

Reset Value

SFR F7h

RSTREQ

00h

RSTREQ

Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset.

bit 0

Extended Interrupt Priority (EIP)

Reset Value

SFR F8h

PWDI

PX5

PX4

PX3

PX2

E0h

PWDI

Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt.

bit 4

0 = The watchdog interrupt is low priority.

1 = The watchdog interrupt is high priority.

PX5

External Interrupt 5 Priority. This bit controls the priority of external interrupt 5.

bit 3

0 = External interrupt 5 is low priority.

1 = External interrupt 5 is high priority.

PX4

External Interrupt 4 Priority. This bit controls the priority of external interrupt 4.

bit 2

0 = External interrupt 4 is low priority.

1 = External interrupt 4 is high priority.

PX3

External Interrupt 3 Priority. This bit controls the priority of external interrupt 3.

bit 1

0 = External interrupt 3 is low priority.

1 = External interrupt 3 is high priority.

PX2

External Interrupt 2 Priority. This bit controls the priority of external interrupt 2.

bit 0

0 = External interrupt 2 is low priority.

1 = External interrupt 2 is high priority.

MSC1210 Datasheet(PDF) 78 Page - Texas Instruments

MSC1210 Datasheet(HTML) 78 Page - Texas Instruments

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