MSC1210 datasheet(14/83 Pages) TI

14 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

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PIN DESCRIPTIONS (continued)

PIN #

DESCRIPTION

NAME

PSEN,

OSCCLK,

MODCLK

Program store enable. Connected to optional external memory as a chip enable. PSEN provides an active low pulse.

In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode.

PSEN is held HIGH for parallel programming mode and LOW for serial programming. This pin can also be selected

(when not using external memory) to output the oscillator clock, modulator clock, HIGH, or LOW. Care should be

taken so that loading on this pin does not inadvertently cause the device to enter programming mode.

ALE

PSEN

Program Mode Selection

Normal operation (User Application mode)

Parallel programming

Serial programming

Reserved

ALE

Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted

at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is

skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to

define serial or parallel programming mode. ALE is held HIGH for parallel programming mode and LOW for parallel

programming. This pin can also be selected (when not using external memory) to output HIGH or LOW. Care should be

taken so that loading on this pin does not inadvertently cause the device to enter programming mode.

External Access Enable: EA must be externally held LOW at the end of RESET to enable the device to fetch code

from external program memory locations starting with 0000h. No internal pull-up on this pin.

46, 47, 49−54

P0.0−P0.7

Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Refer to P1DDR, SFR AEh−AFh.

46, 47, 49−54

P0.0−P0.7

PORT 0.x

Alternate Name

Alternate Use

P0.0

AD0

Address/Data bit 0

P0.1

AD1

Address/Data bit 1

P0.2

AD2

Address/Data bit 2

P0.3

AD3

Address/Data bit 3

P0.4

AD4

Address/Data bit 4

P0.5

AD5

Address/Data bit 5

P0.6

AD6

Address/Data bit 6

P0.7

AD7

Address/Data bit 7

55, 56, 59−64

P1.0−P1.7

Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. Refer to P1DDR, SFR AEh−AFh.

55, 56, 59−64

P1.0−P1.7

PORT 0.x

Alternate Name(s)

Alternate Use

P1.0

T2 input

P1.1

T2EX

T2 external input

P1.2

RxD1

Serial port input

P1.3

TxD1

Serial port output

P1.4

INT2/SS

External Interrupt / Slave Select

P1.5

INT3/MOSI

External Interrupt / Master Out−Slave In

P1.6

INT4/MISO

External Interrupt / Master In−Slave Out

P1.7

INT5/SCK

External Interrupt / Serial Clock

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