ELANSC520 datasheet(106/440 Pages) AMD

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Write Buffer and Read Buffer Register

8-2

Élan™SC520 Microcontroller Register Set Manual

SDRAM Buffer Control (DBCTL)

Memory-Mapped

MMCR Offset 40h

This register controls all the read buffer read-ahead and write buffer functions.

Note: A programmable reset does not preserve this register’s state.

Bit Definitions

Bit

Reserved

RAB_ENB

WB_WM[1–0]

WB_FLUSH

WB_ENB

Reset

00000000

R/W

RSV

R/W

R/W!

R/W

Bit

Name

Function

–5

Reserved

This bit field should be written to 0 for normal system operation.

RAB_ENB

Read-Ahead Feature Enable

This bit is used to enable the read-ahead feature of the read buffer.

0 = The read-ahead feature is disabled.

1 = The read-ahead feature is enabled. If the master request is a burst cycle (two or more

doublewords), when the current cache line is fetched from SDRAM and stored in the read

buffer, the following cache line is also prefetched to take advantage of space locality.

If the master request is not a burst cycle, only the rest of the current cache line is fetched

from SDRAM into the read buffer.

When enabled, the read-ahead feature applies for all bursted read requests from either the

Am5x86 CPU or the PCI bus. (The GP bus DMA controller does not perform bursted reads.)

During SDRAM sizing or test, disabling the read-ahead feature might improve performance of

the sizing or test algorithm. Because most such algorithms test various non-contiguous points

in SDRAM, excessive read-ahead thrashing can result. Although this does

not result in false

indications, it can result in a slight performance degradation of the test algorithm.

After the SDRAM sizing or test process is complete, the user is free to enable the read-ahead

feature of the read buffer when desired.

3-2

WB_WM[1–0]

Write Buffer Watermark

This bit field specifies the write buffer’s watermark setting (i.e., the amount of allocated buffer

space above which the write buffer initiates a write to SDRAM).

00 = 28 doublewords (default)

01 = 24 doublewords

10 = 16 doublewords

11 = 8 doublewords

As data is written into the write buffer, a new rank of storage is allocated unless the written

data can be merged or collapsed into previous ranks. When a write cycle results in a rank

allocation that exceeds the watermark setting, the write buffer requests service from the

SDRAM controller to initiate write transfers to SDRAM.

A higher watermark setting allows the write buffer to fill higher (acquire more master write

data) before requesting SDRAM service, resulting in a greater chance of write data merging

or collapsing. This is desirable if a large amount of incomplete doubleword writes (i.e., byte,

word or three-byte writes) is expected from either the Am5x86 CPU, PCI bus, or GP bus DMA.

A lower watermark setting can be used if more complete doublewords are expected, and so

merging or collapsing of data is less likely. A lower watermark causes the write buffer to

request SDRAM service at a lower threshold, reducing the chance of filling the write buffer.

ELANSC520 Datasheet(PDF) 106 Page - Advanced Micro Devices

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