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ELANSC520 Datasheet(PDF) 110 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 110 Page - Advanced Micro Devices

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ROM/Flash Controller Registers
9-2
Élan™SC520 Microcontroller Register Set Manual
BOOTCS Control (BOOTCSCTL)
Memory-Mapped
MMCR Offset 50h
Register Description
This register contains configuration information about the location (i.e., SDRAM bus or GP bus), width, operation
mode, and timing of the boot ROM that is attached to the ÉlanSC520 microcontroller BOOTCS signal.
Bit Definitions
15
14
13
12
11
10
9
8
Bit
Reserved
DGP
WIDTH[1–0]
MODE
Reserved
Reset
000???00
R/W
RSV
R
R
R/W
RSV
7
6
5
4
3
2
1
0
Bit
Reserved
SUB_DLY[1–0]
Reserved
FIRST_DLY[2–0]
Reset
00110111
R/W
RSV
R/W
RSV
R/W
Bit
Name
Function
15
–13
Reserved
Reserved
This bit field should be written to 0 for normal system operation
12
DGP
BOOTCS Device SDRAM/GP Bus Select
This bit reflects the location of the boot ROM device that is enabled with the BOOTCS signal.
This bit’s value is latched from the CFG2 pinstrap when the PWRGOOD pin is asserted. The
ROM can be connected to either the SDRAM data bus or to the GP bus.
0 = ROM is on the GP bus.
1 = ROM is on the SDRAM data bus.
11
–10
WIDTH[1–0]
BOOTCS Device Width Select
This bit field reflects the width of the boot ROM. This bit field’s value is latched from the
CFG1
–CFG0 pinstraps when the PWRGOOD pin is asserted.
00 = ROM is 8 bits wide.
01 = ROM is 16 bits wide.
10 = ROM is 32 bits wide.
11 = ROM is 32 bits wide (same as 10b).
9MODE
BOOTCS Device Mode
This bit is used to configure the mode of the boot ROM device.
0 = ROM is non-page mode.
1 = ROM is page mode.
8
–6
Reserved
Reserved
This bit field should be written to 0 for normal system operation
5
–4
SUB_DLY[1–0]
BOOTCS Device Delay for Subsequent Access
This bit field is used to configure the number of wait states for all page-mode accesses to the
ROM that are subsequent to the first access. This bit field applies only if the MODE bit is 1.
00 = 0 wait states
01 = 1 wait state
10 = 2 wait states
11 = 3 wait states



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