ELANSC520 datasheet(112/440 Pages) AMD

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ROM/Flash Controller Registers

9-4

Élan™SC520 Microcontroller Register Set Manual

ROMCS1 Control (ROMCS1CTL)

Memory-Mapped

MMCR Offset 54h

This register contains configuration information about the location (i.e., SDRAM bus or GP bus), width, operation

mode, and timing of the ROM devices that are attached to the ÉlanSC520 microcontroller ROMCS1 signal.

Bit Definitions

Bit

Reserved

DGP

WIDTH[1–0]

MODE

Reserved

Reset

00000000

R/W

RSV

R/W

RSV

Bit

Reserved

SUB_DLY[1–0]

Reserved

FIRST_DLY[2–0]

Reset

00110111

R/W

RSV

R/W

RSV

R/W

Bit

Name

Function

–13

Reserved

This bit field should be written to 0 for normal system operation.

DGP

Chip Select 1 Device SDRAM/GP Bus Select

This bit is used to configure the location of the ROM devices that are enabled by ROMCS1.

The ROM can be connected either to the SDRAM data bus or to the GP bus.

0 = ROM is on the GP bus.

1 = ROM is on the SDRAM data bus.

–10

WIDTH[1–0]

Chip Select 1 Device Width Select

This bit field is used to configure the width of the ROM selected by ROMCS1.

00 = ROM is 8 bits wide.

01 = ROM is 16 bits wide.

10 = ROM is 32 bits wide.

11 = ROM is 32 bits wide.

9MODE

Chip Select 1 Device Mode

This bit is used to configure the mode of the ROM selected by ROMCS1.

0 = ROM is non-page mode.

1 = ROM is page mode.

–6

Reserved

This bit field should be written to 0 for normal system operation.

–4

SUB_DLY[1–0]

Chip Select 1 Device Delay for Subsequent Accesses

This bit field is used to configure the number of wait states for all page-mode accesses to the

ROM that are subsequent to the first access. This bit field applies only if the MODE bit is 1.

00 = 0 wait states

01 = 1 wait state

10 = 2 wait states

11 = 3 wait states

Reserved

This bit field should be written to 0 for normal system operation.

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