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ELANSC520 Datasheet(PDF) 142 Page - Advanced Micro Devices |
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ELANSC520 Datasheet(HTML) 142 Page - Advanced Micro Devices |
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142 / 440 page  GP DMA Controller Registers 11-10 Élan™SC520 Microcontroller Register Set Manual GP-DMA Channel 0 Extended Page (GPDMAEXTPG0) Memory-Mapped MMCR Offset D86h Register Description This register provides the extended page address for Channel 0. Bit Definitions Programming Notes The extended page address is used in conjunction with the memory address and the page address registers for the associated channel to make up a 28-bit address (A27–A0). The Channel 0 extended page address bit field (DMA0ADR[27–24]) does not increment or decrement during DMA because this channel does not support enhanced mode. 7 6 5 4 3 2 1 0 Bit Reserved DMA0ADR[27 –24] Reset 00000000 R/W RSV R/W Bit Name Function 7–4 Reserved Reserved This bit field should be written to 0 for normal system operation. 3–0 DMA0ADR [27–24] DMA Channel 0 Extended Page Address This bit field specifies the highest four memory address bits (A27–A24) for Channel 0. |
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