ELANSC520 datasheet(140/440 Pages) AMD

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GP DMA Controller Registers

11-8

Élan™SC520 Microcontroller Register Set Manual

GP-DMA Resource Channel Map B (GPDMAEXTCHMAPB)

Memory-Mapped

MMCR Offset D84h

This register indicates the channel mapping for the internal serial port request signals: txdrq2–txdrq1 and rxdrq2–

rxdrq1.

Bit Definitions

Bit

TXDRQ2_CHSEL[3–0]

TXDRQ1_CHSEL[3–0]

Reset

11111111

R/W

Bit

RXDRQ2_CHSEL[3–0]

RXDRQ1_CHSEL[3–0]

Reset

11111111

R/W

Bit

Name

Function

15–12

TXDRQ2_

CHSEL[3–0]

TXDRQ2 Channel Mapping

Map the txdrq2 and txdack2 internal signals to a GP-DMA channel:

0000 = Channel 0

0001 = Channel 1

0010 = Channel 2

0011 = Channel 3

All other values are treated as unconnected.

11–8

TXDRQ1_

CHSEL[3–0]

TXDRQ1 Channel Mapping

Map the txdrq1 and txdack1 internal signals to a GP-DMA channel:

0000 = Channel 0

0001 = Channel 1

0010 = Channel 2

0011 = Channel 3

All other values are treated as unconnected.

7–4

RXDRQ2_

CHSEL[3–0]

RXDRQ2 Channel Mapping

Map rxdrq2 and rxdack2 internal signals to a GP-DMA channel:

0000 = Channel 0

0001 = Channel 1

0010 = Channel 2

0011 = Channel 3

All other values are treated as unconnected.

ELANSC520 Datasheet(PDF) 140 Page - Advanced Micro Devices

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