ELANSC520 datasheet(136/440 Pages) AMD

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GP DMA Controller Registers

11-4

Élan™SC520 Microcontroller Register Set Manual

GP-DMA Control (GPDMACTL)

Memory-Mapped

MMCR Offset D80h

This register provides control for the enhanced mode and selects the clock frequency.

Bit Definitions

Programming Notes

Bit

CH7_ALT_

SIZE

CH6_ALT_

SIZE

CH5_ALT_

SIZE

CH3_ALT_

SIZE

CLK_MODE

Reserved

ENH_

MODE_

ENB

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

CH7_ALT_SIZE

Alternate Size for Channel 7

0 = Channel 7 is 16 bits wide.

1 = Channel 7 is 8 bits wide.

This bit field is ignored if the ENH_MODE_ENB bit is 0.

CH6_ALT_SIZE

Alternate Size for Channel 6

0 = Channel 6 is 16 bits wide.

1 = Channel 6 is 8 bits wide.

This bit field is ignored if the ENH_MODE_ENB bit is 0.

CH5_ALT_SIZE

Alternate Size for Channel 5

0 = Channel 5 is 16 bits wide.

1 = Channel 5 is 8 bits wide.

This bit field is ignored if the ENH_MODE_ENB bit is 0.

CH3_ALT_SIZE

Alternate Size for Channel 3

0 = Channel 3 is 8 bits wide.

1 = Channel 3 is 16 bits wide.

This bit field is ignored if the ENH_MODE_ENB bit is 0.

Note that the Channel 3 default size differs from the Channel 5–7 default size.

Do not set the CH3_ALT_SIZE bit if an internal UART is mapped to Channel 3 via the

GPDMAEXTCHMAPB register (see page 11-8).

3–2

CLK_MODE

Clock Mode

00 = Operate the GP bus DMA controller at 4 Mhz.

01 = Operate the GP bus DMA controller at 8 Mhz.

10 = Operate the GP bus DMA controller at 16 Mhz.

11 = Reserved.

The frequencies shown here are nominal. The exact GP bus DMA frequency is derived by

dividing the microcontroller’s 33-MHz crystal input, which can be 33.000 or 33.333 MHz.

Reserved

This bit field should be written to 0 for normal system operation.

ENH_MODE_

ENB

Enhanced Mode Enable

0 = Disable enhanced GP-DMA mode (use normal GP-DMA mode).

1 = Enable enhanced GP-DMA mode.

ELANSC520 Datasheet(PDF) 136 Page - Advanced Micro Devices

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