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ELANSC520 Datasheet(PDF) 134 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 134 Page - Advanced Micro Devices

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GP DMA Controller Registers
11-2
Élan™SC520 Microcontroller Register Set Manual
GP-DMA Channel 6 Extended Transfer
Count
GPDMAEXTTC6
D92h
page 11-19
GP-DMA Channel 7 Extended Transfer
Count
GPDMAEXTTC7
D93h
page 11-20
Buffer Chaining Control
GPDMABCCTL
D98h
page 11-21
Buffer Chaining Status
GPDMABCSTA
D99h
page 11-22
Buffer Chaining Interrupt Enable
GPDMABSINTENB
D9Ah
page 11-24
Buffer Chaining Valid
GPDMABCVAL
D9Bh
page 11-25
GP-DMA Channel 3 Next Address Low
GPDMANXTADDL3
DA0h
page 11-26
GP-DMA Channel 3 Next Address High
GPDMANXTADDH3
DA2h
page 11-27
GP-DMA Channel 5 Next Address Low
GPDMANXTADDL5
DA4h
page 11-28
GP-DMA Channel 5 Next Address High
GPDMANXTADDH5
DA6h
page 11-29
GP-DMA Channel 6 Next Address Low
GPDMANXTADDL6
DA8h
page 11-30
GP-DMA Channel 6 Next Address High
GPDMANXTADDH6
DAAh
page 11-31
GP-DMA Channel 7 Next Address Low
GPDMANXTADDL7
DACh
page 11-32
GP-DMA Channel 7 Next Address High
GPDMANXTADDH7
DAEh
page 11-33
GP-DMA Channel 3 Next Transfer Count Low GPDMANXTTCL3
DB0h
page 11-34
GP-DMA Channel 3 Next Transfer Count High GPDMANXTTCH3
DB2h
page 11-35
GP-DMA Channel 5 Next Transfer Count Low GPDMANXTTCL5
DB4h
page 11-36
GP-DMA Channel 5 Next Transfer Count High GPDMANXTTCH5
DB6h
page 11-37
GP-DMA Channel 6 Next Transfer Count Low GPDMANXTTCL6
DB8h
page 11-38
GP-DMA Channel 6 Next Transfer Count High GPDMANXTTCH6
DBAh
page 11-39
GP-DMA Channel 7 Next Transfer Count Low GPDMANXTTCL7
DBCh
page 11-40
GP-DMA Channel 7 Next Transfer Count High GPDMANXTTCH7
DBEh
page 11-41
Table 11-2
GP-DMA Direct-Mapped Registers
Register Name
Mnemonic
I/O Address
Page Number
Slave DMA Channel 0 Memory Address
GPDMA0MAR
0000h
page 11-42
Slave DMA Channel 0 Transfer Count
GPDMA0TC
0001h
page 11-43
Slave DMA Channel 1 Memory Address
GPDMA1MAR
0002h
page 11-44
Slave DMA Channel 1 Transfer Count
GPDMA1TC
0003h
page 11-45
Slave DMA Channel 2 Memory Address
GPDMA2MAR
0004h
page 11-46
Slave DMA Channel 2 Transfer Count
GPDMA2TC
0005h
page 11-47
Slave DMA Channel 3 Memory Address
GPDMA3MAR
0006h
page 11-48
Slave DMA Channel 3 Transfer Count
GPDMA3TC
0007h
page 11-49
Slave DMA Channel 0–3 Status
SLDMASTA
0008h
page 11-50
Slave DMA Channel 0–3 Control
SLDMACTL
0008h
page 11-51
Slave Software DRQ(n) Request
SLDMASWREQ
0009h
page 11-53
Slave DMA Channel 0–3 Mask
SLDMAMSK
000Ah
page 11-54
Slave DMA Channel 0–3 Mode
SLDMAMODE
000Bh
page 11-55
Slave DMA Clear Byte Pointer
SLDMACBP
000Ch
page 11-57
Table 11-1
GP-DMA MMCR Registers (Continued)
Register Name
Mnemonic
MMCR Offset
Page
Number



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