ELANSC520 datasheet(137/440 Pages) AMD

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GP DMA Controller Registers

Élan™SC520 Microcontroller Register Set Manual

11-5

GP-DMA Memory-Mapped I/O (GPDMAMMIO)

Memory-Mapped

MMCR Offset D81h

This register provides the selection of an I/O device (enabled by the GPIORD and GPIOWR signals) or a memory-

mapped I/O device (enabled by the GPMEMRD or GPMEMWR signals) for each channel.

Bit Definitions

Programming Notes

A bit field in this register (GPDMAMMIO) is ignored if the corresponding channel is mapped to an internal UART via

the GPDMAEXTCHMAPB register (see page 11-8).

Bit

DMA7_

MMAP

DMA6_

MMAP

DMA5_

MMAP

Reserved

DMA3_

MMAP

DMA2_

MMAP

DMA1_

MMAP

DMA0_

MMAP

Reset

00000000

R/W

RSV

R/W

Bit

Name

Function

7DMA7_MMAP

Memory-Mapped Device for DMA Channel 7

0 = DMA Channel 7 connects to a direct-mapped I/O device.

1 = DMA Channel 7 connects to a memory-mapped device.

6DMA6_MMAP

Memory-Mapped Device for DMA Channel 6

0 = DMA Channel 6 connects to a direct-mapped I/O device.

1 = DMA Channel 6 connects to a memory-mapped device.

5DMA5_MMAP

Memory-Mapped Device for DMA Channel 5

0 = DMA Channel 5 connects to a direct-mapped I/O device.

1 = DMA Channel 5 connects to a memory-mapped device.

Reserved

This bit field should be written to 0 for normal system operation.

3DMA3_MMAP

Memory-Mapped Device for DMA Channel 3

0 = DMA Channel 3 connects to a direct-mapped I/O device.

1 = DMA Channel 3 connects to a memory-mapped device.

2DMA2_MMAP

Memory-Mapped Device for DMA Channel 2

0 = DMA Channel 2 connects to a direct-mapped I/O device.

1 = DMA Channel 2 connects to a memory-mapped device.

1DMA1_MMAP

Memory-Mapped Device for DMA Channel 1

0 = DMA Channel 1 connects to a direct-mapped I/O device.

1 = DMA Channel 1 connects to a memory-mapped device.

0DMA0_MMAP

Memory-Mapped Device for DMA Channel 0

0 = DMA Channel 0 connects to a direct-mapped I/O device.

1 = DMA Channel 0 connects to a memory-mapped device.

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