DA9021 datasheet(137/142 Pages) DIALOG

137 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Company confidential

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

137 of 142

24 Layout guidelines

24.1 General recommendations

● Appropriate trace width and amount of vias should be used for all power supply paths.

● Too high trace resistances can prevent the system from proper operation, for example efficiency

and current ratings of switch mode converters and charger might be degraded. Furthermore the

PCB might be exposed to thermal hot spots, which can lead to critical overheating due to the

positive temperature coefficient of copper.

● Special care must be taken to the DA9021 pad connections. The traces of the outer row should

be connected with the same width as the pads and should become wider as soon as possible.

For supply pins in the second row connection in an inner layer is recommended (depending on

the maximum current two or more vias might be required).

● A common ground plane should be used, which allows proper electrical and thermal

performance. Noise sensitive references like the VREF capacitor and IREF resistor should be

referred to a silent ground which is connected at a star point underneath or close to the DA9021

main ground connection.

● Generally all power tracks with discontinuous and / or high currents should be kept as short as

possible.

● Noise sensitive analogue signals like feedback lines or crystal connections should be kept away

from traces carrying pulsed analogue or digital signals. This can be achieved by separation

(distance) or shielding with quiet signals or ground traces.

24.2 System supply and charger

● Trace resistance of the VBUS_PROT bypass capacitor to VCENTER must be minimised to allow

proper operation of the charge and system current control.

● If an external pMOS transistor is used to bypass the internal active diode, its connection trace

resistance has to be kept to a minimum.

● The placement of the distributed capacitors at VDDOUT must ensure that all VDD inputs,

especially to the buck converters and LDOs, are connected to a bypass capacitor close to the

pads. It is recommended to place at least two 1 µF capacitors close to the LDO supply pads and

at least one 10 µF close to the buck VDD rail.

● Using a local power plane underneath the chip for VDDOUT can be considered.

● Adequate heat sink areas should be used for at least one terminal of the external overvoltage

protection and / or active diode FETs.

24.3 LDOs and switched mode supplies

● Transient current loops area of the switched mode converters should be minimised.

● The common references (VREF capacitor, IREF resistor) should be placed close to DA9021,

cross coupling to any noisy digital or analogue trace must be avoided.

● Output capacitors of the LDOs should be placed close to the output pins. Small capacitors (for

example 100 nF) are also required to be close to the input pins of the supplied devices.

● Care must be taken that no current is carried on feedback lines (VBUCKxx).

24.4 Crystal oscillator

● The crystal and its load capacitors should be placed as close as possible to the IC with short and

symmetric traces.

● The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the

lines are buried between two ground layers, surrounded by additional ground traces.

DA9021 Datasheet(PDF) 137 Page - Dialog Semiconductor

DA9021 Datasheet(HTML) 137 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL