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AD9136-EBZ Datasheet(PDF) 3 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 117 page  Data Sheet AD9135/AD9136 Rev. C | Page 3 of 117 Register Maps and Descriptions....................................................82 Device Configuration Register Map.........................................82 Device Configuration Register Descriptions ..........................88 Outline Dimensions......................................................................116 Ordering Guide .........................................................................117 REVISION HISTORY 5/2017—Rev. B to Rev. C Changes to Table 25 ........................................................................30 Changes to Table 73 ........................................................................74 3/2017—Rev. A to Rev. B Changed 10.64 Gbps to 12.4 Gbps, 2.76 Gbps to 3.1 Gbps, and 5.52 Gbps to 6.2 Gbps................................................... Throughout Changes to Table 4 ............................................................................7 Change to Device Revision Parameter; Table 14 ...............................25 Changes to Functional Overview of the SERDES PLL Section......37 Changes to Figure 46 ......................................................................38 Change to Register 0x006, Table 84 ..............................................82 Change to Address 0x006, Table 85 ..............................................88 7/2015—Rev. 0 to Rev. A Changed Functional Block Diagram Section to Typical Application Circuit Section..............................................................1 Changes to General Description Section .......................................1 Changed Detailed Functional Block Diagram Section to Functional Block Diagram Section.................................................4 Changes to Offset Drift Parameter, Table 1 ...................................5 Deleted Reference Voltage Parameter, Table 1 ..............................5 Changed 1× Interpolation Mode Parameter to 1× Interpolation Mode, JESD Mode 8, 8 SERDES Lanes Parameter, Table 1 .........5 Changes to Output Voltage (VOUT) Logic High Parameter, Output Voltage (VOUT) Logic Low Parameter, JESD204B Serial Interface Speed Minimum Parameter, and SYSREF± Frequency Parameter, Table 2 .............................................................................6 Changes to Table 4 ............................................................................7 Changes to Interpolation Parameter, Table 6 ................................8 Changed Junction Temperature Parameter to Operating Junction Temperature, Table 10 ....................................................11 Changes to Terminology Section ..................................................17 Changes to Figure 34 Caption and Figure 37 Caption...............21 Changes to Device Revision Parameter, Table 14 .......................25 Changes to Overview Section, Table 15, Table 16, and Table 17.............................................................................................26 Changes to Step 3: Transport Layer Section and Table 19.........27 Changes to Table 20 and Table 21 .................................................28 Changes to Step 7: Optional Features Section.............................29 Added Table 25; Renumbered Sequentially.................................30 Changes to DAC PLL Setup Section, Table 26, and Table 27 ......30 Changes to Table 28 and CurrentLink Section............................31 Added DAC Power-Down Setup Section ....................................31 Changes to Table 30 ........................................................................32 Changes to Table 32 ........................................................................33 Changes to Table 36 and Figure 44 ...............................................36 Changes to Table 37 ........................................................................37 Added SERDES PLL Fixed Register Writes Section and Table 38.............................................................................................37 Changes to Table 39 ........................................................................38 Changes to Figure 47 and Data Link Layer Section ...................39 Added Figure 50; Renumbered Sequentially...............................40 Changes to Table 45 and Table 46.................................................49 Changes to Figure 61 ......................................................................51 Changes to Figure 62 ......................................................................52 Changes to Figure 63 ......................................................................53 Changes to Figure 64 ......................................................................54 Changes to Figure 65 ......................................................................56 Changes to Figure 66 ......................................................................57 Changes to Power Supply Recommendations Section...............61 Added Figure 68 ..............................................................................62 Changes to Figure 72 ......................................................................64 Changes to Data Format Section and Table 61 ...........................65 Changes to Figure 76 ......................................................................66 Changed 0x13D[7:0] to 0x13D[3:0], Table 62.............................67 Changes to Group Delay Section ..................................................67 Changes to DC Test Mode Section ...............................................95 Deleted Table 70; Renumbered Sequentially...............................71 Moved Figure 78 and Table 68 ......................................................71 Added DAC PLL Fixed Register Writes Section and Table 69.............................................................................................72 Changes to Clock Multiplication Section ....................................73 Added Loop Filter Section and Charge Pump Filter Section...... 73 Added Temperature Tracking Section and Table 73 ..................74 Changes to Starting the PLL Section and Figure 82...................74 Changes to Transmit DAC Operation Section............................75 Changes to Start-Up Sequence Section, Table 77, and Table 78.............................................................................................79 Changes to Table 80 and Table 81.................................................80 Changes to Table 82 and Table 83.................................................81 Changes to Table 84 ........................................................................82 Changes to Table 85 ........................................................................88 Deleted Lookup Tables for Three Different DAC PLL Reference Frequencies Section and Table 83 to 85 .....................................112 Added Figure 92 ............................................................................116 Updated Outline Dimensions......................................................116 Changes to Ordering Guide.........................................................117 9/2014—Revision 0: Initial Version |
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