AD9136-EBZ datasheet(22/117 Pages) AD

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AD9135/AD9136

Data Sheet

Rev. C | Page 22 of 117

THEORY OF OPERATION

The AD9135/AD9136 are 11-/16-bit, dual DACs with a SERDES

interface. Figure 2 shows a detailed functional block diagram of

the AD9135/AD9136. Eight high speed serial lanes carry data at

a maximum speed of 12.4 Gbps, and a 2120 MSPS input data rate

to each DAC. Compared to either LVDS or CMOS interfaces, the

SERDES interface simplifies pin count, board layout, and input

clock requirements to the device.

The clock for the input data is derived from the device clock

(required by the JESD204B specification). This device clock can

be sourced with a PLL reference clock used by the on-chip PLL

to generate a DAC clock or a high fidelity direct external DAC

sampling clock. The device can be configured to operate in one-,

two-, four-, or eight-lane modes, depending on the required

input data rate.

The digital datapath of the AD9135/AD9136 offers four

interpolation modes (1×, 2×, 4×, and 8×) through three half-band

filters with a maximum DAC sample rate of 2.8 GSPS. An inverse

sinc filter is provided to compensate for sinc related roll-off.

The AD9135/AD9136 DAC cores provide a fully differential

current output with a nominal full-scale current of 20 mA. The

full-scale current, IOUTFS, is user adjustable to between 13.9 mA

and 27.0 mA, typically. The differential current outputs are

complementary and are optimized for easy integration with the

Analog Devices the ADRF6720 AQM. The AD9135/AD9136

are capable of multichip synchronization that can both

synchronize multiple DACs and establish a constant and

deterministic latency (latency locking) path for the DACs.

The latency for each of the DACs remains constant from link

establishment to link establishment. An external alignment

(SYSREF±) signal makes the AD9135/AD9136 Subclass 1

compliant. Several modes of SYSREF± signal handling are

available for use in the system.

An SPI configures the various functional blocks and monitors

their statuses. The various functional blocks and the data

interface must be set up in a specific sequence for proper

operation (see the Device Setup Guide section). Simple SPI

initialization routines set up the JESD204B link and are included

in the evaluation board package. The following sections describe

the various blocks of the AD9135/AD9136 in greater detail.

Descriptions of the JESD204B interface, control parameters, and

various registers to set up and monitor the device are provided.

The recommended start-up routine reliably sets up the data link.

AD9136-EBZ Datasheet(PDF) 22 Page - Analog Devices

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