AD9136-EBZ datasheet(97/117 Pages) AD

97 / 117 page

Data Sheet

AD9135/AD9136

Rev. C | Page 97 of 117

Address

Name

Bit No.

Bit Name

Settings

Description

Reset

Access

0x089

DACLOOPFILT3

LF_BYPASS_R3

Bypass R3 Resistor. When this bit is set,

bypass the R3 capacitor (set to 0 pF) when

R3_WORD is set to 0. Set this control to 0x0 for

optimal performance.

0x0

R/W

LF_BYPASS_R1

Bypass R1 Resistor. When this bit is set,

bypass the R1 capacitor (set to 0 pF) when

R1_WORD is set to 0. Set this control to 0x0 for

optimal performance.

0x0

R/W

LF_BYPASS_C2

Bypass C2 Capacitor. When this bit is set,

bypass the C2 capacitor (set to 0 pF) when

C2_WORD is set to 0. Set this control to 0x0 for

optimal performance.

0x0

R/W

LF_BYPASS_C1

Bypass C1 Capacitor. When this bit is set,

bypass the C1 capacitor (set to 0 pF) when

C1_WORD is set to 0. Set this control to 0x0 for

optimal performance.

0x0

R/W

[3:0]

LF_R3_WORD

R3 Control Word. Set this control to 0xE for

optimal performance.

0x8

R/W

0x08A

DACCPCNTRL

[7:6]

RESERVED

Reserved.

0x0

[5:0]

CP_CURRENT

Charge Pump Current Control. Set this control

to 0x12 for optimal performance.

0x20

R/W

0x08B

DACLOGENCNTRL

[7:2]

RESERVED

Reserved.

0x0

[1:0]

LO_DIV_MODE

This range controls the RF clock divider

between the VCO and DAC clock rates. The

options are 4×, 8×, or 16× division. Choose the

LO_DIV_MODE so that 6 GHz < fVCO < 12 GHz

(see the Clock Multiplication section for more

details):

0x2

R/W

DAC clock = VCO/4

DAC clock = VCO/8

DAC clock = VCO/16

0x08C

DACLDOCNTRL1

[7:3]

RESERVED

Reserved.

0x0

[2:0]

REF_DIV_MODE

Reference Clock Division Ratio. This field

controls the amount of division that is done

to the input clock at the CLK+/CLK− pins

before it is presented to the PLL as a reference

clock. The reference clock frequency must be

between 35 MHz and 80 MHz, but the

CLK+/CLK− input frequency can range from

35 MHz to 1 GHz. The user sets this division

to achieve a 35 MHz to 80 MHz PLL reference

frequency. For more details see the Clock

Multiplication section.

0x1

R/W

000

001

010

011

100

0x08D

DACLDOCNTRL2

[7:0]

DAC_LDO

DAC PLL LDO setting. This register must be

written to 0x7B for optimal performance.

0x2B

R/W

0x0E2

CAL_CTRL_GLOBAL

[7:2]

RESERVED

Reserved.

0x0

CAL_START_AVG

Averaged Calibration Start. On rising edge,

calibrate the DACs. Only use if calibrating all

DACs.

0x0

R/W

CAL_EN_AVG

Averaged Calibration Enable. Set prior to

starting calibration with CAL_START_AVG.

While this bit is set, calibration can be

performed, and the results are applied.

0x0

R/W

Enable averaged calibration

AD9136-EBZ Datasheet(PDF) 97 Page - Analog Devices

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