AD9136-EBZ datasheet(47/117 Pages) AD

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Data Sheet

AD9135/AD9136

Rev. C | Page 47 of 117

Link Delay Setup Example, Without Known Delay

If the system delays are not known, the AD9135/AD9136 can

read back the link latency between LMFCRX for each link and

the SYSREF± aligned LMFC. This information is then used to

calculate LMFCVar and LMFCDel, as shown in the Without

Known Delays section.

Figure 59 shows how DYN_LINK_LATENCY_x (Register 0x302

and Register 0x303) provides a readback showing the delay (in

PClock cycles) between LMFCRX and the transition from ILAS

to the first data sample. By repeatedly power cycling and taking

this measurement, the minimum and maximum delays across

power cycles can be determined and used to calculate LMFCVar

and LMFCDel.

The example shown in Figure 59 is demonstrated in the following

steps according to the procedure outlined in the Without Known

Delays section. Note that this example is in Subclass 1 to achieve

deterministic latency, which has a PClockFactor (frame clock rate/

PClockRate) of 2 and uses K = 16; therefore, PClocksPerMF = 8.

In Figure 59, for Link A, Link B, and Link C, the system

containing the AD9135/AD9136 (including the

transmitter) is power cycled and configured 20 times. The

AD9135/AD9136 are configured as described in the Device

Setup Guide. Because the point of this exercise is to

determine LMFCDel and LMFCVar, the LMFCDel is

programmed to 0 and DYN_LINK_LATENCY_x is read

from Register 0x302 and Register 0x303 for Link 0 and

Link 1, respectively. The variation in the link latency over

the 20 runs is shown in Figure 59 in gray.

Link A gives readbacks of 6, 7, 0, and 1. Note that the set of

recorded delay values rolls over the edge of a multiframe at

the boundary K/PClockFactor = 8. Add PClocksPerMF = 8

to low set. Delay values range from 6 to 9.

Link B gives Delay values from 5 to 7.

Link C gives Delay values from 4 to 7.

Calculate the minimum of all Delay measurements across

all power cycles, links, and devices:

MinDelay = min(all Delay values) = 4

Calculate the maximum of all Delay measurements across

all power cycles, links, and devices:

MaxDelay = max(all Delay values) = 9

Calculate the total Delay variation (with guard band)

across all power cycles, links, and devices:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (9 + 1) − (4 − 1) = 10 − 3 = 7 PClock cycles

Calculate the minimum delay in frame clock cycles (with

guard band) across all power cycles, links, and devices:

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

= ((4 − 1) × 2) % 16 = (3 × 2) % 16

= 6 % 16 = 6 frame clock cycles

Write LMFCDel to both Register 0x304 and Register 0x305

for all devices in the system. Write LMFCVar to both

system.

Figure 58. DYN_LINK_LATENCY Illustration

Figure 59. Multilink Synchronization Settings, Derived Method Example

ILAS

DATA

SYSREF

ALIGNED DATA

LMFCRX

DYN_LINK_LATENCY

DYN_LINK_LATENCY_CNT

ALIGNED LANE DATA (A)

DETERMINISTICALLY

DELAYED DATA

LMFCRX

ALIGNED LANE DATA (B)

ALIGNED LANE DATA (C)

FRAME CLOCK

LMFC

PCLK

DATA

ILAS

DATA

ILAS

DATA

ILAS

DATA

ILAS

LMFC_DELAY = 6

(FCLK CYCLES)

LMFC_VAR = 7

(PCLK CYCLES)

AD9136-EBZ Datasheet(PDF) 47 Page - Analog Devices

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