AD9136-EBZ datasheet(32/117 Pages) AD

32 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 32 of 117

SERDES CLOCKS SETUP

This section describes how to select the appropriate Halfrate,

OvSmp, and PLLDiv settings in the Step 4: Physical Layer

section. These parameters depend solely on the lane rate (the

lane rate is established in the JESD204B Setup section).

Table 30. SERDES Lane Rate Configuration Settings

Lane Rate (Gbps)

Halfrate

OvSmp

PLLDiv

1.44 to 3.1

2.88 to 6.2

5.75 to 12.4

Halfrate and OvSmp set how the clock detect and recover (CDR)

circuit samples. See the SERDES PLL section for an explanation

of how that circuit blocks works and the role of PLLDiv in the

block.

EQUALIZATION MODE SETUP

Set EqMode = 1 for a low power setting. Select this mode if the

insertion loss in the printed circuit board (PCB) is less than

12 dB. For insertion losses greater than 12 dB but less than

17.5 dB, set EqMode = 0. More details can be found in the

Equalization section.

LINK LATENCY SETUP

This section describes the steps necessary to guarantee

multichip deterministic latency in Subclass 1 and to guarantee

synchronization of links within a device in Subclass 0. Use this

section to fill in LMFCDel, LMFCVar, and Subclass in the Step 5:

Data Link Layer section. For more information, see the Syncing

LMFC Signals section.

Subclass Setup

The AD9135/AD9136 support JESD204B Subclass 0 and

Subclass 1 operation.

Subclass 1

This mode gives deterministic latency and allows links to be

synced to within ½ DAC clock periods. It requires an external

SYSREF± signal that is accurately phase aligned to the DAC clock.

Subclass 0

This mode does not require any signal on the SYSREF± pins,

which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same

LMFC cycle and that the two DACs must be synchronized to

each other; they are synchronized to an internal clock instead of

to the SYSREF± signal.

Set Subclass to 0 or 1 as desired.

Link Delay Setup

LMFCVar and LMFCDel are used to impose delays such that all

lanes in a system arrive in the same LMFC cycle.

The unit used internally for delays is the period of the internal

processing clock (PClock), whose rate is 1/40th the lane rate.

Delays that are not in PClock cycles must be converted before

they are used.

Some useful internal relationships are defined by

PClockPeriod = 40/LaneRate

PClockPeriod can be used to convert from time to PClock

cycles when needed.

PClockFactor = 4/F (frames per PClock)

PClockFactor is used to convert from units of PClock cycles to

FrameClock cycles, which is needed to set LMFCDel in

Subclass 1.

PClocksPerMF= K/PClockFactor (PClocks per LMFC cycle)

where PClocksPerMF is the number or PClock cycles in a

multiframe cycle.

The values for PClockFactor and PClockPerMF are given per

JESD mode in Table 31.

Table 31. PClockFactor and PClockPerMF

JESD Mode ID

PClockFactor

PClockPerMF (K = 32)

PClockPerMF (K = 16)

N/A1

1 N/A means not applicable.

With Known Delays

With information about all the system delays, LMFCVar and

LMFCDel can be calculated directly.

RxFixed (the fixed receiver delay in PClock cycles) and RxVar

(the variable receiver delay in PClock cycles) can be found in

Table 8. TxFixed (the fixed transmitter delay in PClock cycles)

and TxVar (the variable receiver delay in PClock cycles) can be

found in the data sheet of the transmitter used. PCBFixed (the

fixed PCB trace delay in PClock cycles) can be extracted from

software; because this is generally much smaller than a PClock

cycle, it can also be omitted. For both the PCB and transmitter

delays, convert the delays into PClock cycles.

For each lane,

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

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