AD9136-EBZ datasheet(69/117 Pages) AD

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Data Sheet

AD9135/AD9136

Rev. C | Page 69 of 117

Blanking State Machine (BSM)

The BSM gently ramps data entering the DAC and flushes the

datapath.

On a falling edge of TX_PROTECT (the TXENx signal delayed

by the Tx ENSM), the datapath holds the latest data value and

the digital gain gently ramps from its set value to 0. At the same

time, the datapath is flushed with zeros.

On a rising edge of TX_PROTECT, the TXENx signal is

delayed by the Tx ENSM; data is allowed to flow through the

datapath again and the digital gain gently ramps the data from 0

up to the set digital gain.

Both of these functions are also triggered automatically by the

LMFC sync logic during a rotation to prevent glitching on the

output.

Ramping

For proper ramping, digital gain must be enabled; tie TXENx

high if disabling digital gain.

The step size to use when ramping gain to 0 or its assigned value

can be controlled via the GAIN_RAMP_DOWN_STEP[11:0]

registers (Register 0x142 and Register 0x143) and the

GAIN_RAMP_UP_STEP[11:0] registers (Register 0x140 and

DAC Paging section.

The current BSM state can be read back as shown in Table 65.

Table 65. Blanking State Machine Ramping Readbacks

Value

Description

0x147[7:6]

0b00

Data is being held at midscale.

0b01

Ramping gain to 0. Data ramping to

midscale.

0b10

Ramping gain to assigned value. Data

ramping to normal amplitude.

0b11

Data at normal amplitude.

Blanking State Machine IRQ

Blanking completion is available as an IRQ event.

Use Register 0x021[5] to enable blanking completion for DAC0

and then use Register 0x025[5] to read back its status and reset

the IRQ signal.

Use Register 0x022[5] to enable blanking completion for DAC1

and then use Register 0x026[5] to read back its status and reset

the IRQ signal.

See the Interrupt Request Operation section for more information.

PROTECT_OUTx Generation

PROTECT_OUTx signal. Register 0x11F[2] can be used to invert

the PROTECT_OUTx signal. By default, PROTECT_OUTx is

high when the output is valid. Register 0x013 and Register 0x11F

are paged as described in the DAC Paging section.

Table 66. PROTECT_OUTx Registers

Reg.

Bit

No.

Bit Name

Description

0x013

TX_PROTECT_OUT

1: Tx ENSM triggers

PROTECT_OUT

SPI_PROTECT_OUT

1: SPI_PROTECT

triggers PROTECT_OUT

SPI_PROTECT

Sets SPI_PROTECT

0x11F

PROTECT_OUT_INVERT

Inverts PROTECT_OUTx

DATAPATH PRBS

The datapath PRBS can be used to verify that the AD9135/

AD9136 datapath is receiving and correctly decoding data. The

datapath PRBS verifies that the JESD204B parameters of the

transmitter and receiver match, that the lanes of the receiver are

mapped appropriately, that the lanes have been appropriately

inverted, if necessary, and in general that the start-up routine

has been implemented correctly. The datapath PRBS test is

designed to support input data rates of up to 1060 MHz.

The datapath PRBS is paged as described in the DAC Paging

section. To run the datapath PRBS test, complete the following

steps:

Set up the device in the desired operating mode. See the

Device Setup Guide section for details on setting up the

device.

Send the PRBS7 or PRBS15 data.

Write Register 0x14B[2] = 0 for PRBS7 or 1 for PRBS15.

Write Register 0x14B[1:0] = 0b11 to enable and reset the

PRBS test.

Write Register 0x14B[1:0] = 0b01 to enable the PRBS test

and release reset.

Wait 500 ms.

Check the status by checking the IRQ for DAC0 and DAC1

PRBS as described in the Datapath PRBS IRQ section.

If there are failures, set Register 0x008 = 0x01 to view the

status of DAC0. Set Register 0x008 = 0x02 to view the

status of DAC1.

Read Register 0x14B[6]. Bit 6 is 0 if the selected DAC has

any errors. This must match the IRQ.

10. Read Register 0x14C to read the error count of the selected

DAC.

Note that the PRBS processes 32 bits at a time, and compares

the 32 new bits to the previous set of 32 bits. It detects (and

reports) only 1 error in every group of 32 bits; therefore, the

error count partly depends on when the errors are seen. For

example,

•

Bits: 32 good, 31 good, 1 bad; 32 good (2 errors)

•

Bits: 32 good, 22 good, 10 bad; 32 good (2 errors)

•

Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good

(3 errors)

AD9136-EBZ Datasheet(PDF) 69 Page - Analog Devices

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