AD9136-EBZ datasheet(7/117 Pages) AD

7 / 117 page

Data Sheet

AD9135/AD9136

Rev. C | Page 7 of 117

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SDO to SCLK

Data Valid Window

tDV

CS to SCLK

Setup Time

tSCS

Hold Time

tHCS

1 See Table 3 for detailed specifications for DAC update rate conditions.

2 The maximum speed for 1× and 2× interpolation is limited by the JESD204B interface with increased supply levels. See Table 4 for details.

3 The maximum speed for 4× and 8× interpolation is limited by the DAC core. See Table 4 for details.

4 See Table 4 for detailed specifications for JESD204B speed conditions.

5 REFCLK is the reference clock.

6 K, F, and S are JESD204B transport layer parameters. See Table 43 for the full definitions.

7 See Table 5 for detailed specifications for SYSREF signal to DAC clock timing conditions.

MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

MAXIMUM DAC UPDATE RATE

2×, 4×, and 8× Interpolation

DVDD12, CVDD12 = 1.2 V ± 5%

2.23

GSPS

DVDD12, CVDD12 = 1.2 V ± 2%

2.41

GSPS

DVDD12, CVDD12 = 1.3 V ± 2%

2.80

GSPS

1× Interpolation

DVDD12, CVDD12 = 1.2 V ± 5%

1.81

GSPS

DVDD12, CVDD12 = 1.2 V ± 2%

1.93

GSPS

DVDD12, CVDD12 = 1.3 V ± 2%

2.21

GSPS

JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

HALF RATE

SVDD12 = 1.2 V ± 5%

5.75

11.4

Gbps

SVDD12 = 1.2 V ± 2%

5.75

12.0

Gbps

SVDD12 = 1.3 V ± 2%

5.75

12.4

Gbps

FULL RATE

SVDD12 = 1.2 V ± 5%

2.88

5.98

Gbps

SVDD12 = 1.2 V ± 2%

2.88

6.06

Gbps

SVDD12 = 1.3 V ± 2%

2.88

6.2

Gbps

OVERSAMPLING

SVDD12 = 1.2 V ± 5%

1.44

3.0

Gbps

SVDD12 = 1.2 V ± 2%

1.44

3.04

Gbps

SVDD12 = 1.3 V ± 2%

1.44

3.1

Gbps

AD9136-EBZ Datasheet(PDF) 7 Page - Analog Devices

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