AD9136-EBZ datasheet(46/117 Pages) AD

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AD9135/AD9136

Data Sheet

Rev. C | Page 46 of 117

The method to set the LMFCDel and LMFCVar values is

described in the Link Delay Setup section.

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then LMFCVar

is written into the receive buffer delay (RBD) to absorb all link

delay variation. This ensures that all data samples have arrived

before reading. By setting these to fixed values across runs and

devices, deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from 1 frame clock cycle to K frame clock cycles, whereas the

RBD of the AD9135/AD9136 take values from 0 PClock cycles

to 10 PClock cycles. As a result, up to 10 PClock cycles of total

delay variation can be absorbed. Because LMFCVar is in PClock

cycles, and LMFCDel is in frame clock cycles, a conversion

between these two units is needed. The PClockFactor, or

number of frame clock cycles per PClock cycle, is equal to 4/F.

For more information on this relationship, see the Clock

Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

both Register 0x304 and Register 0x305 for all devices in the

system, and write LMFCVar to both Register 0x306 and

Link Delay Setup Example, with Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel as described in the Link Delay Setup section.

The example shown in Figure 57 is demonstrated in the

following steps according to the procedure outlined in the Link

Delay Setup section. Note that this example is in Subclass 1 to

achieve deterministic latency, which has a PClockFactor (4/F)

of two frame clock cycles per PClock Cycle, and uses K = 32

(frames/multiframe). Because PCBFixed << PClockPeriod,

PCBFixed is negligible in this example and not included in the

calculations.

Find the receiver delays using Table 8.

RxFixed = 17 PClock cycles

RxVar = 2 PClock cycles

Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

transceiver on a Virtex-6 FPGA) states that the delay is

56 ± 2 byte clock cycles.

Because the PClockRate = ByteRate/4 as described in the

Clock Relationships section, the transmitter delays in

PClock cycles are as follows:

TxFixed = 54/4 = 13.5 PClock cycles

TxVar = 4/4 = 1 PClock cycle

Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(17 + 13.5 + 0)

= floor(30.5)

MinDelayLane = 30

Calculate MaxDelayLane as follows:

MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +

TxVar + PCBFixed))

= ceiling(17 + 2 + 13.5 + 1 + 0)

= ceiling(33.5)

MaxDelayLane = 34

Calculate LMFCVar as follows:

LMFCVar = (MaxDelay + 1) − (MinDelay − 1)

= (34 + 1) − (30 − 1) = 35 − 29

LMFCVar = 6 PClock cycles

Calculate LMFCDel as follows:

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

= ((30 − 1) × 2) % 32 = (29 × 2) % 32

= 58 % 32

LMFCDel = 26 frame clock cycles

Write LMFCDel to both Register 0x304 and Register 0x305

for all devices in the system. Write LMFCVar to both

system.

Figure 57. LMFC_DELAY_x Calculation Example

FCLK

LMFC

PCLK

DYN_LINK_LATENCY_CNT

DATA

ALIGNED LANE DATA (A)

ILAS

DATA

DETERMINISTICALLY

DELAYED DATA

ILAS

LMFCRX

LMFC_DELAY_x = 12

(FCLK CYCLES)

DATA

ALIGNED LANE DATA (B)

ILAS

DATA

ALIGNED LANE DATA (C)

ILAS

LMFC_VAR = 6

(PCLK CYCLES)

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