AD9136-EBZ datasheet(12/117 Pages) AD

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AD9135/AD9136

Data Sheet

Rev. C | Page 12 of 117

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 12. Pin Function Descriptions

Pin No.

Mnemonic

Description

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

CLK+

PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.

When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be

ac-coupled.

CLK−

PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.

When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be

ac-coupled.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

SYSREF+

Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled

or dc-coupled.

SYSREF−

Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled

or dc-coupled.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

TXEN0

Transmit Enable for DAC0. CMOS levels are determined with respect to IOVDD.

TXEN1

Transmit Enable for DAC1. CMOS levels are determined with respect to IOVDD.

DVDD12

1.2 V Digital Supply.

DVDD12

1.2 V Digital Supply.

SERDIN0+

Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN0−

Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN1+

Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

PVDD12

CLK+

CLK–

PVDD12

SYSREF+

SYSREF–

PVDD12

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.

PVDD12

TXEN0

TXEN1

DVDD12

SERDIN0+

SERDIN0–

SVDD12

SERDIN1+

SERDIN1–

SVDD12

PROTECT_OUT1

59 PROTECT_OUT0

60 IRQ

61 RESET

62 SDO

63 SDIO

64 SCLK

65 CS

66 IOVDD

PVDD12

GND

DVDD12

SERDIN7+

SERDIN7–

SVDD12

SERDIN6+

SERDIN6–

SVDD12

VTT

SVDD12

VTT

SVDD12

AD9135/AD9136

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