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AD9136-EBZ Datasheet(PDF) 88 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 88 Page - Analog Devices |
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88 / 117 page  AD9135/AD9136 Data Sheet Rev. C | Page 88 of 117 Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W 0x47A IRQVECTOR_MASK BADDIS_ MASK NIT_MASK UCC_ MASK RESERVED INITIALLANESYNC_ MASK BADCHECKSUM _MASK FRAMESYNC_ MASK CODEGRP- SYNC_MASK 0x00 R/W 0x47A IRQVECTOR_FLAG BADDIS_ FLAG NIT_FLAG UCC_FLAG RESERVED INITIALLANESYNC_ FLAG BADCHECKSUM _FLAG FRAMESYNC_ FLAG CODEGRP- SYNC_FLAG 0x00 R 0x47B SYNCASSERTION- MASK BADDIS_S NIT_S UCC_S CMM CMM_ENABLE RESERVED 0x008 R/W 0x47C ERRORTHRES ETH 0xFF R/W 0x47D LANEENABLE LANE_ENA 0x0F R/W 0x47E RAMP_ENA RESERVED ENA_RAMP_ CHECK 0x00 R/W 0x520 DIG_TEST0 RESERVED DC_TEST_ MODE RESERVED 0x1C R/W 0x521 DC_TEST_VALUE0 DC_TEST_VALUE[7:0] 0x00 R/W 0x522 DC_TEST_VALUE1 DC_TEST_VALUE[15:8] 0x00 R/W DEVICE CONFIGURATION REGISTER DESCRIPTIONS Table 85. Device Configuration Register Descriptions Address Name Bit No. Bit Name Settings Description Reset Access 0x000 SPI_INTFCONFA 7 SOFTRESET_M Soft Reset (Mirror). 0x0 R 6 LSBFIRST_M LSB First (Mirror). 0x0 R 5 ADDRINC_M Address Increment (Mirror). 0x0 R 4 SDOACTIVE_M SDO Active (Mirror). 0x0 R 3 SDOACTIVE SDO Active. 0x0 R/W 2 ADDRINC Address Increment. Controls whether addresses are incremented or decremented during multibyte data transfers. 0x0 R/W 1 Addresses are incremented during multibyte data transfers 0 Addresses are decremented during multibyte data transfers 1 LSBFIRST LSB First. Controls whether input and output data are oriented as LSB first or MSB first. 0x0 R/W 1 Shift LSB in first 0 Shift MSB in first 0 SOFTRESET Soft Reset. Setting this bit initiates a reset. This bit is autoclearing after the soft reset is complete. 0x0 R/W 1 Assert soft reset 0x003 CHIPTYPE [7:0] CHIPTYPE The product type is “High Speed DAC”, which is represented by a code of 0x04. 0x4 R 0x004 PRODIDL [7:0] PRODIDL Product Identification Low. 0x44 R 0x005 PRODIDH [7:0] PRODIDH Product Identification High. 0x91 R 0x006 CHIPGRADE [7:4] PROD_GRADE Product Grade. R AD9136 0x6 R AD9135 0x4 R [3:0] DEV_REVISION Device Revision. 0x8 R 0x008 SPI_PAGEINDX [7:2] RESERVED Reserved. 0x0 R [1:0] DAC_PAGE DAC Paging. Selects which DAC is accessed and written to when changing digital features, such as digital gain, dc offset. This paging affects Register 0x013 to Register 0x014, Register 0x034 to Register 0x03D, Register 0x110 to Register 0x124, and Register 0x135 to Register 0x14C. 0x3 R/W 0b01 Read and write DAC0 0b10 Read and write DAC1 0b11 Write both DACs; read DAC0 |
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