AD9136-EBZ datasheet(8/117 Pages) AD

8 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 8 of 117

SYSREF SIGNAL TO DAC CLOCK TIMING SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns

Setup Time

AC-coupled

126

DC-coupled

131

Hold Time

AC-coupled

DC-coupled

119

SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns

Setup Time

AC-coupled

DC-coupled

104

Hold Time

AC-coupled

DC-coupled

SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns

Setup Time

AC-coupled

DC-coupled

Hold Time

AC-coupled

DC-coupled

DIGITAL INPUT DATA TIMING SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.

Table 6.

Parameter

Min

Typ

Max

Unit

LATENCY

Interface

PClock1 cycles

Interpolation

1×

DAC clock cycles

2×

137

DAC clock cycles

4×

251

DAC clock cycles

8×

484

DAC clock cycles

Inverse Sinc

DAC clock cycles

Digital Gain Adjust

DAC clock cycles

POWER-UP TIME

µs

1 PClock is the AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.

AD9136-EBZ Datasheet(PDF) 8 Page - Analog Devices

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