AD9136-EBZ datasheet(96/117 Pages) AD

96 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 96 of 117

Address

Name

Bit No.

Bit Name

Settings

Description

Reset

Access

0x081

SYSREF_ACTRL0

[7:5]

RESERVED

Reserved.

0x0

PD_SYSREF

Power-Down SYSREF Buffer. This bit powers

down the SYSREF receiver. For Subclass 1

operation to work, this buffer must be enabled.

0x1

R/W

HYS_ON

Hysteresis Enabled. This bit enables the

programmable hysteresis control for the

SYSREF receiver. Using hysteresis gives some

noise resistance, but delays the SYSREF±

edge an amount depending on HYS_CNTRL

and the SYSREF± edge rate. The SYSREF±

KOW is not guaranteed when using

hysteresis.

0x0

R/W

SYSREF_RISE

Select DAC Clock Edge to Sample SYSREF.

0x0

R/W

Use falling edge of DAC clock to sample

SYSREF for alignment

Use rising edge of DAC clock to sample

SYSREF for alignment

[1:0]

HYS_CNTRL1

Hysteresis Control Bits[9:8]. HYS_CNTRL is a

10-bit thermometer-coded number. Each bit

set adds 10 mV of differential hysteresis to

the SYSREF receiver.

0x0

R/W

0x082

SYSREF_ACTRL1

[7:0]

HYS_CNTRL0

Hysteresis Control Bits[7:0].

0x0

R/W

0x083

DACPLLCNTRL

RECAL_DACPLL

Recalibrate DAC PLL. On a rising edge of this bit,

recalibrate the DAC PLL.

0x0

R/W

[6:5]

RESERVED

Reserved.

0x0

ENABLE_DACPLL

Synthesizer Enable. This bit enables and

calibrates the DAC PLL.

0x0

R/W

[3:0]

RESERVED

Reserved.

0x0

0x084

DACPLLSTATUS

DACPLL_

OVERRANGE_H

DAC PLL High Overrange. This bit indicates

that the DAC PLL hit the upper edge of its

operating band. Recalibrate.

0x0

DACPLL_

OVERRANGE_L

DAC PLL Low Overrange. This bit indicates

that the DAC PLL hit the lower edge of its

operating band. Recalibrate.

0x0

DACPLL_CAL_

VALID

DAC PLL Calibration Valid. This bit indicates

that the DAC PLL has been successfully

calibrated.

0x0

[4:2]

RESERVED

Reserved.

0x0

DACPLL_LOCK

DAC PLL Lock Bit. This bit is set high by the PLL

when it has achieved lock.

0x0

RESERVED

Reserved.

0x0

0x085

DACINTEGERWORD0

[7:0]

B_COUNT

Integer Division Word. This bit controls the

integer feedback divider for the DAC PLL.

Determine the frequency of the DAC clock by

the following equations (see the Clock

Multiplication section for more details):

0x8

R/W

fDAC

= fREF/(REF_DIVRATE) × 2 × B_COUNT

fVCO

= fREF/(REF_DIVRATE) × 2 × B_COUNT ×

LO_DIV_MODE

Minimum value is 6.

0x087

DACLOOPFILT1

[7:4]

LF_C2_WORD

C2 Control Word. Set this control to 0x6 for

optimal performance.

0x8

R/W

[3:0]

LF_C1_WORD

C1 Control Word. Set this control to 0x2 for

optimal performance.

0x8

R/W

0x088

DACLOOPFILT2

[7:4]

LF_R1_WORD

R1 Control Word. Set this control to 0xC for

optimal performance.

0x8

R/W

[3:0]

LF_C3_WORD

C3 Control Word. Set this control to 0x9 for

optimal performance.

0x8

R/W

AD9136-EBZ Datasheet(PDF) 96 Page - Analog Devices

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