AD9136-EBZ datasheet(60/117 Pages) AD

60 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 60 of 117

Monitoring Errors via SYNCOUTx±

When one or more disparity, not in table, or unexpected control

character error occurs, the error is reported on the SYNCOUTx±

pins as per Section 7.6 of the JESD204B specification. The

JESD204B specification states that the SYNCOUTx± signal is

asserted for exactly two frame periods when an error occurs. For

the AD9135/AD9136, the width of the SYNCOUTx± pulse can be

programmed to ½, 1, or 2 PClock cycles. The settings to achieve

a SYNCOUTx± pulse of 2 frame clock cycles are given in Table 57.

Table 57. Setting SYNCOUTx± Error Pulse Duration

1 These register settings assert the SYNCOUTx± signal for 2 frame clock cycle

pulse widths.

Disparity, Not in Table, and Unexpected Control

Character IRQs

For disparity, not in table, and unexpected control character

errors, error count over the threshold events are available as

IRQ events. Enable these events by writing to Register 0x47A[7:5].

The IRQ event status can be read at the same address

(Register 0x47A[7:5]) after the IRQs are enabled.

See the Error Counter and IRQ Control section for information

on resetting the IRQ. See the Interrupt Request Operation

section for more information on IRQs.

Errors Requiring Reinitializing

A link reinitialization automatically occurs when four invalid

disparity characters are received as per Section 7.1 of the

JESD204B

specification. When a link reinitialization occurs, the

resync request is five frames and nine octets long.

The user can optionally reinitialize the link when the error

count for disparity errors, not in table errors, or unexpected

control characters reaches a programmable error threshold. The

process to enable the reinitialization feature for certain error

types is as follows:

Set THRESHOLD_MASK_EN (Register 0x477[3]) = 1.

Note that when this bit is set, unmasked errors do not

saturate at either threshold or maximum value.

Enable the sync assertion mask for each type of error by

writing to the SYNCASSERTIONMASK register

(Register 0x47B[7:5]) according to Table 58.

Program the desired error counter threshold into

ERRORTHRES (Register 0x47C).

For each error type enabled in the SYNCASSERTIONMASK

programmed threshold, SYNCOUTx± falls, issuing a sync

request. Note that all error counts are reset when a link

reinitialization occurs. The IRQ does not reset and must be

reset manually.

Table 58. Sync Assertion Mask

Addr.

Bit No.

Bit Name

Description

0x47B

BADDIS_S

Set to 1 to assert SYNCOUTx±

if the disparity error count

reaches the threshold

NIT_S

Set to 1 to assert SYNCOUTx±

if the not in table error count

reaches the threshold

UCC_S

Set to 1 to assert SYNCOUTx±

if the unexpected control

character count reaches the

threshold

CGS, Frame Sync, Checksum, and ILAS Monitoring

that each stage of the JESD204B link establishment has

occurred. Program Register 0x300[2] = 0 to monitor the status

of the lanes on Link 0, and Register 0x300[2] = 1 to monitor the

status of the lanes on Link 1.

Bit x of CODEGRPSYNCFLAG (Register 0x470) is high if Link

Lane x received at least four K28.5 characters and passed code

group synchronization.

Bit x of FRAMESYNCFLAG (Register 0x471) is high if Link

Lane x completed initial frame synchronization.

Bit x of GOODCHKSUMFLG (Register 0x472) is high if the

checksum sent over the lane matches the sum of the JESD204B

parameters sent over the lane during ILAS for Link Lane x. The

parameters can be added either by summing the individual fields

in registers or summing the packed register. If Register 0x300[6] =

0 (default), the calculated checksums are the lower eight bits of

the sum of the following fields: DID, BID, LID, SCR, L − 1, F − 1,

K − 1, M − 1, N − 1, SUBCLASSV, NP − 1, JESDV, S − 1, and HD.

If Register 0x300[6] = 1, the calculated checksums are the lower

eight bits of the sum of Register 0x400 to Register 0x40C and LID.

Bit x of INITLANESYNCFLG (Register 0x473) is high if Link

Lane x passed the initial lane alignment sequence.

CGS, Frame Sync, Checksum, and ILAS IRQs

Fail signals for CGS, frame sync, checksum, and ILAS are available

as IRQ events. Enable them by writing to Register 0x47A[3:0].

The IRQ event status can be read at the same address

(Register 0x47A[3:0]) after the IRQs are enabled. Write a 1 to

to reset the frame sync IRQ. Write a 1 to Register 0x472 to reset

the checksum IRQ. Write a 1 to Register 0x473 to reset the ILAS

IRQ.

See the Interrupt Request Operation section for more information.

JESD Mode

IDs

PClockFactor

(Frames/PClock)

SYNCB_ERR_DUR

(Register 0x312[5:4]) Setting1

8, 9, 11, 12

0 (default)

10, 13

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