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AD9136-EBZ Datasheet(PDF) 57 Page - Analog Devices |
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AD9136-EBZ Datasheet(HTML) 57 Page - Analog Devices |
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57 / 117 page  Data Sheet AD9135/AD9136 Rev. C | Page 57 of 117 Table 53. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 13 Address Setting Description 0x453 0x00 or 0x80 Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x0: L = 1 lane per link (L = 2 on transmit side)1 0x454 0x01 Register 0x454[7:0] = 0x01: F = 2 octets per frame 0x455 0x0F or 0x1F Register 0x455[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe 0x456 0x00 Register 0x456[7:0] = 0x00: M = 1 converter per link (M = 2 on transmit side)1 0x457 0x0F Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459[7:5] = 0x1: set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample per converter) per frame 0x45A 0x00 Register 0x45A[7] = 0: HD = 0; Register 0x45A[4:0] = 0x00: always set CF = 0 0x46C 0x11 Register 0x46C[7:0] = 0x0F: deskew Link Lane 0 and Link Lane 4 0x476 0x02 Register 0x476[7:0] = 0x02: F = 2 octets per frame 0x47D 0x11 Register 0x47D[7:0] = 0x01: enable Link Lane 0 and Link Lane 4 1 Note that for Mode 11 through Mode 13, the M and L parameters programmed on the receive side do not match the parameters on the transmit side. The parameters on the transmit side reflect the true number of converters and lanes per link. Figure 66. JESD204B Mode 13 Data Deframing 2 OCTETS PER LANE (F = 2) 16-BIT NIBBLE GROUP (N = 16) 1 SAMPLE PER CONVERTER PER FRAME (S = 1) DAC0 DAC1 SERIAL JESD204B DATA (L = 2) SAMPLES NOT SPLIT ACROSS LANES (HD = 0) NIBBLE GROUP 1 CONVERTER 1, SAMPLE 0 LANE 1, OCTET 0 LANE 1, OCTET 1 2 CONVERTERS (M = 2) NIBBLE GROUP 0 CONVERTER 0, SAMPLE 0 LANE 0, OCTET 0 LANE 0, OCTET 1 |
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