AD9136-EBZ datasheet(9/117 Pages) AD

9 / 117 page

Data Sheet

AD9135/AD9136

Rev. C | Page 9 of 117

LATENCY VARIATION SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.

Table 7.

Parameter

Min

Typ

Max

Unit

DAC LATENCY VARIATION

SYNC On

PLL Off

DAC clock cycles

PLL On

−1

DAC clock cycles

JESD204B INTERFACE ELECTRICAL SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 8.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

JESD204B DATA INPUTS

Input Leakage Current

TA = 25°C

Logic High

Input level = 1.2 V ± 0.25 V, VTT = 1.2 V

µA

Logic Low

Input level = 0 V

−4

µA

Unit Interval

714

Common-Mode Voltage

VRCM

AC-coupled, VTT = SVDD121

−0.05

+1.85

Differential Voltage

R_VDIFF

110

1050

VTT Source Impedance

ZTT

At dc

Ω

Differential Impedance

ZRDIFF

At dc

100

120

Ω

Differential Return Loss

RLRDIF

Common-Mode Return Loss

RLRCM

DIFFERENTIAL OUTPUTS (SYNCOUTx±)2

Output Differential Voltage

VOD

Normal Swing Mode

192

235

High Swing Mode

341

394

Output Offset Voltage

VOS

1.19

1.27

DETERMINISTIC LATENCY

Fixed

PClock3 cycles

Variable

PClock3 cycles

SYSREF± to LOCAL MULTIFRAME

COUNTER (LMFC) DELAY

DAC clock cycles

1 As measured on the input side of the ac coupling capacitor.

2 IEEE Standard 1596.3 LVDS compatible.

3 PClock is an AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.

AD9136-EBZ Datasheet(PDF) 9 Page - Analog Devices

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