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GS3590 Datasheet(PDF) 60 Page - Semtech Corporation

Part # GS3590
Description  Bidirectional 3G-SDI Re-timing Adaptive Cable Equalizer/Cable Driver
PDF  118 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3590 Datasheet(HTML) 60 Page - Semtech Corporation

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GS3590
Final Data Sheet Rev.4
PDS-061414 September 2017
60 of 118
Semtech
Proprietary & Confidential
www.semtech.com
If signal loopback is required by the application, the Trace and Cable Drivers can be
active at the same time by setting CTRL_LOOPBACK_ENA to 1. Setting
CTRL_LOOPBACK_ENA to 1 overrides any setting in
CFG_TRDR_MUTE_WHEN_CABLE_DRIVER, but not the state settings configured in
Section 4.8.7.1 to Section 4.8.7.3.
4.8.8 Output Waveform Specifications
The Duty Cycle Distortion (DCD) of the serial digital differential outputs is less than 12ps.
DCD is defined as the difference in the width of an output logic “1” versus that of output
logic “0” as measured at the 50% point of the output waveform.
The DCD of the serial digital single ended outputs is less than 30ps.
Figure 4-22: Traditional Waveform Definition of DCD
4.9 GPIO Controls
There are four configurable GPIO pins which can independently be configured as inputs
or outputs. Each GPIO has a default function which can be re-configured through the
host interface.
If there is a conflict between the internal register configuration of a given device
function and the logic-level applied to a GPIO pin that is configured to control that same
device function, the GPIO logic-level takes precedence over the internal register
configuration. The logic HIGH and LOW levels of the GPIO[3:0] pin to which LOS is
connected are specified by the EIA/JESD8-5A standard for 1.8V operation.
For a list of available functions and configuration details of GPIO[3:0], please refer to the
GPIO Configuration Registers in Section 5.
50% point
t
high
t
low
DCD
waveform = thigh - tlow



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