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Time Base Timer
PRELIMINARY V1.8
11
Figure 5.
Time Base Timer
8.2.
Time Base Timer Control Register (TBCR)
Address
B1H
Bit Addr.
BIT
7
6
5
4
3
2
1
0
NAME
TBEN
TBCLR
TBFS2
TBFS1
TBFS0
HTST
MTST
Definition
TB timer
ENable
TB
counter
CLeaR
TB timer
input
Frequency
Select
bit-2
TB timer
input
Frequency
Select
bit-1
TB timer
input
Frequency
Select
bit-0
Hour
Clock
Test
Minute
Clock
Test
Reserved
Reset
Value
0
0
0
0
0
0
0
0
F1sec
F1min
F1hour
F125ms
Fsys/12
Ffast/24
Ffast/27
Ffast/210
MUX
TBDAT
Comparator
TBCNT
8-bit
or
Match
Tbint
TBEN
TBCLR
TBFS
[7]
[6]
[5:3]
DATA BUS
ena
up-counter