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SS1102C Datasheet(PDF) 92 Page - List of Unclassifed Manufacturers

Part # SS1102C
Description  Integrated MCU with Spread-Spectrum Transceiver (SST)
PDF  129 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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External Interrupts
PRELIMINARY V1.8
87
15. External Interrupts
15.1.
Overview
There are 2 external interrupts, IRQ1 and IRQ2. The external interrupts share pins with
the Port-X.0 to Port-X.1. To use an IRQi (i = 0 to 1) pin as an external interrupt pin, the
pin must be assigned to input mode by the Port-X Control Register. The external
interrupt sources can be programmed to be negative edge activated, low level activated,
positive edge activated, or both edge activated by setting or clearing bit IRQi1 and
IRQi0 in Register XICRn (External Interrupt Control Register). If IRQiA = 0 and
IRQiB = 0, IRQi is negative edge triggered. In this mode if successive samples of the
IRQi pin show a high in one sample and a low in the next cycle, interrupt request flag,
IRQiF, will be set. Flag bit IRQiF then requests the interrupt. This bit must be cleared
by software in the interrupt service routine. The IRQiF bit can be also set or cleared by
software. If IRQiA = 1 and IRQiB = 0, IRQi is positive edge triggered. In this mode if
successive samples of the IRQi pin show a low in one sample and a high in the next
cycle, interrupt request flag IRQiF will be set. Flag bit IRQiF then requests the interrupt.
If IRQiA = 1 and IRQiB = 1, IRQi is both (positive or negative) edge triggered. In this
mode if successive samples of the IRQi pin show difference between one sample and
the next sample, interrupt request flag IRQiF will be set. Flag bit IRQiF then requests
the interrupt. If IRQiA = 0 and IRQiB = 1, IRQi is low level activated. If IRQi is low,
interrupt request flag IRQiF will be set. In this case, software can not clear IRQiF if the
pin IRQi is still low. Thus, make sure the pin IRQi becoming high level (inactivate
state) in the interrupt service routine.
]
TABLE 62.
IRQi (i = 0 to 5) Mode Selection
15.2.
Interrupt Control Block
The SS1102C provides 13 interrupt sources (2 external interrupt and 11 internal
interrupt). There are two external interrupt pins, IRQ1 to IRQ2. Following peripheral
blocks may generate interrupt request, Watch-Dog Timer, Time Base Timer, Capture
Timer-1 to 2, SPI, LBD, TXFIFO, RXFIFO, Signaling Word transmit or received, S/N
Ratio, and Lock. These interrupt sources are divided into 5 groups.
IRQiA: IRQiB
Active Edge or Level
[IRQiA: IRQiB] = 00
Negative Edge
[IRQiA: IRQiB] = 01
Low Level
[IRQiA: IRQiB] = 10
Positive Edge
[IRQiA: IRQiB] = 11
Both (Positive or Negative) Edge



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