Capture Timers 1/2
PRELIMINARY V1.8
17
Figure 7.
Capture Timer 1 in Up-Down Count Mode
9.4.
Capture Mode
If the CT1MD[2:0] bits in the CT1CR are 001, 010, or 011, the C-Timer1 will operate
in the Capture Mode. Counting clock selection feature is the same with the Auto-Reload
Mode.
If the CT2MD[1:0] bits in the CT2CR are 01, 10, or 11, the C-Timer2 will operate in the
Capture Mode. Counting clock selection feature is the same with the Auto-Reload
Mode.
After the CT1EN (or CT2EN) bit is set to high, the 16-bit counter (CT1CNTH &
CT1CNTL or CT2CNTH & CT2CNTL) will start to count up the negative edge of a
selected input clock. In Capture Mode, CT1CNTH & CT1CNTL (or CT2CNTH &
CT2CNTL) act as a 16-bit up-counter that can be cleared by the CT1CNTLR (or
CT2CNTLR) bit. The CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) is a
modulo-65536 counter (from 0 to 65535). The overflow signal will always set the
CT1INT (or CT2INT) bit and CT1OVUN bit in CT1SR to high. The overflow signal
also set the CT1OV to high. The CT1INT (or CT2INT) bit can be cleared by a C-Timer
Interrupt Acknowledge or software, and CT1OV and CT1OVUN can be cleared by
reading the CT1SR. Another Capture-Timer1 interrupt will not be generated if
CT1OVUN is still not being cleared.
Fsys/12
Ffast/24
Ffast/25
Ffast/27
Ffast/210
Ffast/214
Ffast/218
CPTRU1
MUX
CT1CNTH:CT1CNTL
16-bit up down-
CTint
ena
CTEN CTCNTLRCTFS CTMD
[7]
[6]
[5:3]
[2:0]
8-bit data bus
counter
CPTRD1
ena
overflow or
underflow
CT1OVUN
CT1O V
CT1UN
overflow
[7]
CT1SR
CT1CR
underflow
[6]
[5]
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