98 / 129 page
External Interrupts
PRELIMINARY V1.8
93
TABLE 65.
Definition of INT2
15.3.1
Interrupt Source Enable Registers (ISE0, ISE1, ISE2)
TABLE 66.
Definition of ISE0
Address
F8H
Bit Addr.
FFH
FEH
FDH
FCH
FBH
FAH
F9H
F8H
BIT
7
6
5
4
3
2
1
0
NAME
TBINT
CT1INT
CT2INT
LBDINT
WDINT
Definition
Reserved
bit
Time-
Base
Timer
Interrupt
1:
Request
0: No
Capture
Timer-1
Interrupt
1:
Request
0: No
Capture
Timer-2
Interrupt
1:
Request
0: No
Reserved
bit
Reserved
bit
LBD
Interrupt
1:
Request
0: No
Watch-
Dog Timer
Interrupt
1:
Request
0: No
Reset Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Write
by Hardware
Set by
TB-Timer
Overflow
Set by
C Timer-1
Overflow
Set by
C Timer-2
Overflow
Set by
LBD
Detect
Set by
WDTimer
Overflow
Address
D7H
Bit Addr.
None
BIT
7
6
5
4
3
2
1
0
NAME
EIRQ2F
EIRQ1F
Definition
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
Enable
IRQ2F
1: Enable
0: Disable
Enable
IRQ1F
1: Enable
0: Disable
Reset Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R
R
R
R
R
R
R/W
R/W
Write
by Hardware
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
