SS1102C datasheet(52/129 Pages) ETC1

52 / 129 page

Direct Sequence Spread Spectrum Baseband Modem (SSTM)

PRELIMINARY V1.8

Figure 18.

Timing for half-duplex Operation

The receiver will not be locked lock until the initial acquisition process has been

completed. This process typically takes from 60-110 bits depending on the condition of

the radio link. It is imperative, therefore, for the packet to carry framing information so

that the beginning and end of the packet can be detected (for example, a high-speed

synchronous data link protocol such as HDLC provides its own framing structure in the

packets it transmits). In addition, sufficient preamble bits must be transmitted prior to

actual data transmission so that the receiver will be locked and ready to deliver data

when actual data arrives.

Note that there is a key difference between full-duplex and half-duplex operation. In a

half-duplex operation, there is no concept of Master or Slave. The SSTM will start

transmitting “1”s (if there is no data in the TXFIFO) or data when the user asserted the

RTS_N control bit. The SSTM Receiver will receive “1”s or data, accordingly.

The SSTM Receiver will generate the interrupt signals and deliver “1”s to the MCU

even if there is no transmission process at all. Those “1”s are a content of the RXFIFO.

12.11. Reading the Signaling Word and S/N Data

The Signaling Word (SW) and S/N register data are updated periodically by the SSTM.

Once a Signaling Word or a S/N value has been loaded onto the register by the SSTM,

the interrupt pending RXSW bit is asserted. Once the interrupt bit has been asserted, no

RTS_N

Invalid RX data

~60 Bits

Receiver Acquisition

~60 Bits

TRANSMITTER

RECEIVER

* Drawing not to scale.

LOCK

SS1102C Datasheet(PDF) 52 Page - List of Unclassifed Manufacturers