Direct Sequence Spread Spectrum Baseband Modem (SSTM)
PRELIMINARY V1.8
49
Name
Addr
ess
Bank
Select
CI_l[1]
Inde
x
Write/
Read
Functions
CI_h
8F
0
[7:0]
WR/
RD
CI_h[0]: Master/Slave Selection bit (1/0)
CI_h[3:1]:Number of errors allowed in the UW
CI_h[4]:LockSMon
CI_h[5]:Data Mode Selection/Test Mode (1/0)
CI_h[6]: Half/Full Duplex Select (1/0)
CI_h[7]:RTS_N bit (0 to enable)
CI_l
8E
0
[7:0]
WR/
RD
CI_l[0]: Normal Mode
CI_l[1]: High/Low Bank Select
CI_l[3:2]:Width of ESD Window
CI_l[4]: Set the Width of “Central Region”
CI_l[5]: DPLL Accumulator 1 Reset
CI_l[7:6]: Set the Width of “Detection Window”
RDI
FE
0
[7:0]
WR/
RD
Write data for TXFIFO
Read data for RXFIFO
IE
C8
0
[7:0]
WR
** Writes to this register will have no effect.
The Interrupts IS[0] to IS[3] and IS[7] for the SSTM are con-
nected directly to the interrupt module in the SS1102C.
Thus enable can be performed in the interrupt module. The
status for the remaining interrupts can be read in the SSTM
IS status register.
IS
C8
0
[7:0]
RD
IS[0]: RXSW Interrupt Pending
IS[1]: S/N Interrupt Pending
IS[2]: TXFIFO Threshold Interrupt Pending
IS[3]: RXFIFO Threshold Interrupt Pending
IS[4]: TXFIFO Underflow Pending
IS[5]: TXFIFO Overflow Pending
IS[6]: RXFIFO Overflow Pending
IS[7]: TXSW Transmit Interrupt Pending
LCK
9E
0
[1:0]
RD
LCK[0]: LOCK Achieved for Full Duplex or
NMODE Achieved for Half Duplex
LCK[1]: RLOCK Achieved for Full Duplex
TXSW
AE
0
[7:0]
Write
Signaling Word to be transmitted
RXSW
AE
0
[7:0]
Read
Signaling Word received
S/N
AF
0
[7:0]
Read
Signal/Noise indicator
PNA0
BE
0
[7:0]
WR/
RD
PNA[7:0]
PNA1
CE
0
[7:0]
WR/
RD
PNA[15:8]
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