Capture Timers 1/2
20
PRELIMINARY V1.8
TABLE 11.
The Description of CT1CR/CT2CR
Name
Bit
Description (Note: n = 1 or 2)
CT1EN
CT2EN
7
C-Timer ENable bit
[Bit Status: 0 (Initial Value)]
A selected input clock is halted. The CTnCNTH & CTnCNTL keeps counting
value.
[Bit Status: 1]
A selected input clock is run. The CTnCNTH & CTnCNTL counts up the negative
edge of the selected clock.
CT1CNTLR
CT2CNTLR
6
CTn counter CLeaR bit
If this bit is written with high, the CTnCNTH & CTnCNTL (16-bit up-counter) of
the C-Timer will be cleared to 0000H. Writing low will not affect anything. When
read, a low(0) will be always read.
CT1FS[5:3]
CT2FS[5:3]
5 to 3
C-Timer input clock Frequency Select bits
[Bit Status: 000 (Initial Value)] Fsys/12
[Bit Status: 001] Ffast/2
4
[Bit Status: 010] Ffast/2
5
[Bit Status: 011] Ffast/2
7
[Bit Status: 100] Ffast/2
10
[Bit Status: 101] Ffast/2
14
[Bit Status: 110] Ffast/2
18
[Bit Status: 111] CPTRU1 or CPTRU2
To use the CPTRU1 or CPTRU2 pin as an Event Input or Up Down-Count Input,
the pin should be assigned to input mode by a port control register.
CT1MD[2:0]
CT2MD[2:0]
2 to 0
C-Timer MoDe select bits
[Bit Status: 000 (Initial Value)]
Auto-Reload Mode
[Bit Status: 001]
Positive Edge Detect Capture Mode
[Bit Status: 010]
Negative Edge Detect Capture Mode
[Bit Status: 011]
Any Edge (Positive or Negative) Detect Capture Mode
[Bit Status: 1XX] (Capture-Timer1 only)
Up Down-Count Mode
CT2MD[2] of C-Timer2 is unused.
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