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SPI (Serial Peripheral Interface)
PRELIMINARY V1.8
33
Figure 12.
SPI Master-Slave Interconnection
11.5.
SPI Control Register (SPICR)
TABLE 24.
Definition of SPICR
Address
F1H
Bit Addr.
BIT
7
6
5
4
3
2
1
0
NAME
SPIE
SPE
CPOL
CPHA
SPR1
SPR0
Definition
SPI Inter-
rupt
ENable
SPI System
Enable bit
Reserved
bit
Reserved
bit
SPI Clock
Polarity
Select
SPI Clock
Phase
SPI Clock
Rate Select
Bit 1
SPI Clock
Rate Select
Bit 0
Reset Value
0
0
0
1
0
0
0
0
Read/
Write by
Software
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Write by
Hardware
SPI Clock
Generator
SPI Shift Register
SPI Shift Register
Buffer
SCK
SCK
Buffer
Output
Port
SS
MI
MISO
MO
MOSI
Master
Slave
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