99 / 129 page  External Interrupts 94 PRELIMINARY V1.8 TABLE 67. Definition of ISE1 Address E7H Bit Addr. None BIT 7 6 5 4 3 2 1 0 NAME ESWINT ESNRINT ESPIINT ERXFINT ETXFINT ELockINT Definition Reserved bit Enable Signaling Word Interrupt 1: Enable 0: Disable Enable S/N Ratio Interrupt 1: Enable 0: Disable Enable SPI Interrupt 1: Enable 0: Disable Reserved bit Enable RXFIFO Interrupt 1: Enable 0: Disable Enable TXFIFO Interrupt 1: Enable 0: Disable Enable LOCK Interrupt 1: Enable 0: Disable Reset Value 0 0 0 0 0 0 0 0 Read/Write by Software R/W R/W R/W R/W R/W R/W R/W R/W Write by Hardware Address F7H Bit Addr. None BIT 7 6 5 4 3 2 1 0 NAME ETBINT ECT1INT ECT2INT ELDBINT EWDINT Definition Reserved bit Enable Time- Base Timer Interrupt 1: Enable 0: Disable Enable Capture Timer-1 Interrupt 1: Enable 0: Disable Enable Capture Timer-2 Interrupt 1: Enable 0: Disable Reserved bit Reserved bit Enable LDB Interrupt 1: Enable 0: Disable Enable Watch- Dog Timer Interrupt 1: Enable 0: Disable Reset Value 0 0 0 0 0 0 0 0 Read/Write by Software R/W R/W R/W R/W R/W R/W R/W R/W Write by Hardware |
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