SS1102C Special Modes
98
PRELIMINARY V1.8
16. SS1102C Special Modes
16.1.
TEST ROM (Using Auxiliary RAM)
The TEST ROM for the SS1102C is initiated by driving the TST and P4.2 pin to a high
and the P4.3 pin to a low during reset. This will cause the CPU to fetch opcodes from
the onchip auxiliary data ram. The ram is currently 256 bytes. The P4.3 and P4.2 pins
will return to the to the general purpose I/O functions after reset has gone inactive.
To load the RAM with opcodes the user should use the “External Memory mode”
described below to load the auxiliary data ram using either MOVC or MOVX
commands. Then the device can be reset and placed in the test ROM mode without
losing the ram data.
16.2.
EMULATION MODE
The SS1102C has 22 extra bond pads on the die which are emulation interface I/O. The
pins and their functions are listed below. The emulation mode is entered by driving the
ENICE pin low. This causes the SS1102C to redirect program and data memory fetches
through the emulation interface.
TABLE 72.
Extra Pins Function
In normal operation the SS1102C will fetch opcodes from the internal program memory
and data memory is accessed to internal IRAM and, with the MOVX command, to
internal XRAM and external data RAM. When emulation mode is entered the internal
IRAM continues to be accessed as in normal mode but the program memory fetches and
the MOVX data memory fetches are both done through the emulation interface. At the
emulation interface the internal program memory fetch is made to look like an external
PIN
TYPE
FUNCTION
EAD7-0
I/O
Low byte address and data I/O
EA15-8
OUTPUT
High byte address
EPSEN
OUTPUT
Program store enable for program memory read active low
EALE
OUTPUT
Address latch enable
ENWR
OUTPUT
Data memory write active low
ENRD
OUTPUT
Data memory read active low
ENICE
INPUT
In circuit emulation mode input active low
ENMON
INPUT
Monitor mode active low
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