Time Base Timer
12
PRELIMINARY V1.8
TABLE 4.
Definition of TBCR
TABLE 5.
Description of TBCR
Read/
Write by
Software
R/W
R/W
Always 0
read.
R/W
R/W
R/W
R/W
R/W
R
Write by
Hardware
Name
Bit
Description
TBEN
7
TB timer ENable bit
[Bit Status: 0 (Initial Value)]
A selected input clock is halted. The TBCNT keeps the counter value.
[Bit Status: 1]
A selected input clock runs. The TBCNT counts up the negative edge of the selected clock.
TBCLR
6
TB counter CLeaR bit
If this bit is written with high, the TBCNT (8-bit up-counter) of the TB Timer will be cleared to
00H. Writing low will not affect anything. When read, a low(0) will be always read.
TBFS[5:3]
5 to 3
TB timer input clock Frequency Select bits
[Bit Status: 000 (Initial Value)] F1SEC
[Bit Status: 001] F1MIN
[Bit Status: 010] F1HOUR
[Bit Status: 011] F125mS
[Bit Status: 100] Fsys/12
[Bit Status: 101] Ffast/2
4
[Bit Status: 110] Ffast/2
7
[Bit Status: 111] Ffast/2
10
HTST
2
Hour clock Test bit
[Bit Status: 0 (Initial Value)]
Normal hour clock signal is used for F1hour.
[Bit Status: 1]
A test mode using XSout (32.768KHz) for F1hour.
Note: The bit can only be set either under FastAll or FastPeri modes.
User should write a 0 to this bit.
MTST
1
Minute clock Test bit
[Bit Status: 0 (Initial Value)]
Normal minute clock signal is used for F1min.
[Bit Status: 1]
A test mode using the XSout (32.768KHz) for F1min .
Note: The bit can only be set either under FastAll or FastPeri modes.
User should write a 0 to this bit.
TBINT
0
Reserved bits
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