Direct Sequence Spread Spectrum Baseband Modem (SSTM)
42
PRELIMINARY V1.8
signaling word transmission, TDAT is the time delay for data transmission, and T∆ is the
internal logic delay. For a 32 Kbps full duplex data rate signal, with a master oscillator
(MO) of 16.384 MHz, this system delay translates into 5.625 msec.
Figure 15.
System Delay
12.9.
Timing Information
12.9.1
Full Duplex Operations
In Full Duplex mode chips communicating with each other should have RTS_N
enabled. A chip which is configured as a Master starts the acquisition procedure and
data transmission. A Slave waits for a valid spread spectrum signal to arrive.
The SSTM transmits and receives data through TXFIFO and RXFIFO buffers. The
writing and reading of data to and from the FIFOs are supported by the internal
SS1102C bus. The synchronization of the data exchange between the microprocessor
and the SSTM is provided by the use of the internal interrupt signals RXFIFO and
TXFIFO connected to the interrupt module of the SS1102C. An interrupt indicating
when LOCK is achieved is also sent to the interrupt module.
The interrupts and transfer of data with the FIFOs is allowed once LOCK is achieved.
When an SSTM interrupt is sent to the SS1102C interrupt module the corresponding
bits of interrupt status register in the interrupt module or the SSTM module indicate that
the TXshl bit from TXFIFO or/and RXshh bit from RXFIFO is set. TXFIFO interrupt
will be active if TXFIFO index is below the programmed TXshl and will remain active
until the index is above the TXshh. The RXFIFO interrupt will be active if RXFIFO
index is above the programmed RXshh and will remain active until the index is below
the RXshl. Thus the microprocessor must write data into the SSTM for transmission
when the TXFIFO interrupt is asserted by the TXFIFO, and it must read data from the
SSTM when the RXFIFO interrupt is asserted by the RXFIFO. Difference in value
between thresholds high and low should be at least two bytes. The best performance is
achieved when the TXshl is 5 and TXshh is 22.
When TXFIFO interrupts indicates that the TXshl control bit is initiated, data bytes
should be written into the TXFIFO. To avoid the overflow of the TXFIFO and loss of
data, the maximum number of bytes to be written should not be more than (30 - TXshl)
bytes. The size of the burst is 288 bits or 30 bytes. If there is no enough user’s data to fill
Tdelay
DAT
PR UW SW
DAT
PR UW SW
G2
G1
DAT
PR UW SW
Master
Slave
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